Analysis Of SET Sensitivity For Voltage-controlled Oscillator And Radiation Hardening By Design

As well known,it is the active circuits that it is seriously sensitive to the radiation effect in out-space. Because of the impact of high energy particle, the temporal or permanence fault will occur in the space vehicle. As the critical portion, the response characteristic of analog circuits to radiation effect is a hot spot in that research filed, and the same to the radiation hardened by design.As the indispensability component in an orbiter, Voltage Controlled Oscillator, which works at the highest frequency spectrum, is very sensitive to the radiation effect, especially to the single event transients. Most studies of radiation effect in voltage controlled oscillators focused on the theory of device at present. It caused a big dissipation of period and cost. Moreover, the response characteristics of various VCO topology vary dramatically, leading to the different PLL noise patterns when affected by SETs.To investigate the SET response and hardening technique for VCO, the thesis covers the research aspects as below:1. A general SET analysis model for VCO is developed, namely the SET Sensitivity Function (SSF), which is based on the linear time variant model by characterizing SET effect as an impulse current. Thus the SET response characteristic of VCO is quantitatively transferred to the phase deviationφmax. This work hammers the theoretical basis for PLL SET model when the SET is brought in VCO model.2. Further, the research on how factors affect the SET response in the symmetrical load VCO, such as injection energy, hit location, hit time, working frequency and so on. Analyze the SET failure mechanism in the circuit level.3. A SET hardened VCO circuit based on Radiation Harden By Design technique is introduced. The simulation results indicate that the hardened VCO decreases the possibility to be hit by SET by 67%, while the SET sensitivity reduced to 65% of unhardened.4. The layout design technique of analog circuits is researched by refining the match and protection for the layout to prevent from the interference of noise. The post -layout simulation indicates a good performance of the SET hardened VCO.5. A VCO chip is fabricated in 0.18μm CMOS technology, which comprises a symmetrical load VCO and a SET harden VCO. Practical tests indicate that the two VCOs work well, and the preparation for radiation tests is on the way.