SET Simulation Analysis Research Of The Comparator And Amplifier

As technology feature size of integrated circuit continues to shrink towards deep sub micron,more and more advanced microelectronic circuits and systems have been used in spacecraft,thus set a higher demand on radiation resistance performance of the devices and circuits.The reduced dimension and increased clock frequency dramatically increase the intensity of single-event transients(SET)in analog circuits.The SET in analog circuits has attracted much attention of scholar in domestic and abroad.Based on the importance of operational amplifier and comparator in analog and analog mixed signal(AMS)circuits,this thesis chooses a generic two-stage CMOS operational amplifier and the regenerative clock control comparator as the main research objects.After understanding the mechanism and the influence of SET in analog circuits,the two-stage CMOS operational amplifier and the regenerative clock control comparator are designed and simulated under SMIC 0.13 ?m technology.In this thesis,a SET simulation analysis was carried out for the two-stage CMOS operational amplifier.Based on the influence of SET on circuit characteristics like gain,phase margin and unity-gain bandwidth,we determined that the output nodes of the two stages are the most sensitive nodes in the amplifier.On this basis,the influence of different parameters on SET sensitivity of the two-stage CMOS operational amplifier was discussed.It comes to a conclusion that the low gain and high bandwidth operational amplifier has a better SET response than the high gain and low bandwidth operational amplifier.Increasing the bandwidth and reducing the gain are beneficial to mitigate the effects of SET on circuits.In this thesis,a SET sensitivity analysis was carried out for the regenerative clock control comparator.According to the response in every single stage,the SET sensitive nodes in single every stage of the comparator are determined.On this basis,the influence of SET on the overall circuit of comparator is obtained by analyzing whether the logic error happens on the final output of comparator.The simulation results show that the sensitive nodes at different stages of comparator may not affect the function of the comparator.However,the insensitive nodes at different stages of comparator may also cause function error of the comparator.The SET sensitivity of the comparator depends on the working condition and the input.In this thesis,a system level SET mitigation method which is suitable for analog circuits was innovatively proposed.The method takes the advantage of charge sharing,based on redundancy selection,can correctly choose the output of the circuit which is not hit by energetic particle as the final output,thereby reducing the effect of SET on analog circuits.In this thesis,a SET mitigation study was carried out for the two-stage CMOS operational amplifier and the regenerative clock control comparator.For the two-stage CMOS operational amplifier,the system level SET mitigation method proposed in this thesis is adopted.The simulation results show that the SET mitigation method presented in this thesis can make the output voltage transient pulse amplitude average 78.4% lower,pulse width,on average,by 98.24%.The improvement of the pulse width can even across an order of magnitude.In particular,it can effectively reduce the pulse width,thus verifies the effectiveness of our proposed SET mitigation method.In view of the comparator circuit,this thesis adopts the method of Triple Modular Redundancy(TMR)for reinforcement design and the reinforcement effect is verified.Aiming at the problem of analog single event transient,a system level mitigation method was proposed in this thesis.We use our proposed method to reinforce the two-stage CMOS operational amplifier,and the reinforcement effect are compared with DCC and SNACC,we found that the system level mitigation method presented in this thesis has a better reinforcement effect than DCC and SNACC,In particular,the pulse width can be reduced effectively.The SET mitigation method proposed in this thesis provides a new way of thinking for analog circuits redundant RHBD method.