The Timing Optimization Of High Performance DSP Core Physical Design

With the reduction of technology, it's very difficult for timing of the large scale integrated circuits to converge in physical design. So it's very significant to research the timing optimization of high performance DSP physical design. This paper studied timing optimization on the basis of the core's physical design. The core is the key to the performance of YHFT-Y in 40 nm process. The paper elaborated some new optimized methods for the design goal of 1GHz under the SS corner. The new methods and innovations are as follows:1), This paper researched the method of manual semi-custom. It mainly included the circuit design of the part registers, repeaters planning, pre-placed in layout and the application of the fast pulse trigger array. By this means, the relative critical paths of register file were eliminated completely.2), This paper studied the placement of hard macro, the guide of soft module, the pre-placed gate and the part critical path's cells etc in the floorplan of hierarchical design. This paper proposed the novel me thod for clock tree synthesis, which is dividing section and local optimization. By this means, the clock tree was balanced and its delay was smaller than the traditional C TS. Clock skew met design demand and timing got improved.3), When design scale is large, it's too hard to make the logical number of every stage equal. The front and bank of some critical paths had timing margin. Hence, this paper proposed the new ECO flow with useful clock skew to optimize timing. This paper researched the methods how to effectively replace the low threshold cells. It combined the EDA tool, PT analysis result and third-party tools to make timing converge and control the number of replacing.