Research Of LDPC Encoding And Decoding In Space Communication And Realization

Low-density parity-check code, based on a sparse parity check matrix structure, is a linear block code with excellent performance which is close to the Shannon error limit. The LDPC code is widely applied in the space communications with long transmission distance, severe signal attenuation, and limited signal transmission power. However, the traditional process of the LDPC encoding is highly complicated, which restricted its widespread applications. In this thesis, the LDPC encoder and the decoder with high performance and low complexity, based on the space communication envirornment, is investigated. The main work is as follows:Firstly, based on the former research of the LDPC construction and the encoder algorithm, a quasi dual-diagonal structure constructed parity-check matrix method is proposed. This method reconsiders the quasi dual-diagonal structure of the IEEE802.16 e standard. Besides in the basic configuration, it also eliminates the constraints of the check matrix expansion factor. Therefore, the proposed construction of the LDPC codes decreases the complexity of encoding. It can be applied to a variety of scenarios of the space communication, especially those with code length and rate combinations. As an example, the(16384,8192) LDPC code is selected for the matrix structure. Meanwhile, the fast encoding algorithm and encoding circuit design are also discussed.Then, based on the recommended CCSDS for deep space and near-Earth application of standards several LDPC code, it is studied that the influence of the decode algorithm, iteration times, the length of the coding, and the rate to the bit error rate(BER). The purpose is to find out the decode algorithm which fits for the application of the hardware. By the improvement of the typical message-transfering approach, the serial message-passing mechanism is applied to the normalized least-sum decoding algorithms. Compared to the conventional parallel algorithms, the new method reduces the iteration and computation, improves the decoding convergence, decreases the amount of data storage, which is more suitable for the decoder hardware. The numerical simulation of the BER of(16384,8192) LDPC code demonstrates that the proposed serial decode algorithm can achieve the excellent error rate performance.Finally, the decoder FPGA hardware of the(16384,8192) LDPC code is constructed. Through the analysis of the factors, such as the maximum number of iterations, normalized parameters, and the ways of the data quantification, the decode hardware of the(16384,8192) LDPC code is completed based on the top-level FPGA circuit and functional modules design. The design method in this thesis can achieve high decoding performance and the low implementation complexity LDPC decoder, which is suitable for the space communications.