Research On Multi-layer And Non-blocking Ring NoC

With the advancement of semiconduct technology, the increasing cores are integrated in one chip. Multi-core and even many-core become the current trends in micro-processor design. As cores are increasing, Traditional bus interconnection faces the limitations of bandwidth and scalability as well as power consumption, etc. Network On-chip with its efficient and scalable communication ability gradually replaced the bus as the main way of the communication between cores. However, traditional No C introduces large amount of hardware overheads, which becomes the bottleneck of the performance and the scalability of multi-core processors. In order to reduce the hardware overheads and improve the performance, we propose a multi-layer, non-blocking ring No C architecture and evaluate its performance and overheads. The ring No C architecture is based on the demand of high performance and low power consumption for a DSP. Moreover, we also propose a multi-layer, non-blocking hierarchical ring No C architecture for many-core and even hundred-core micro-processors. Hence, this thesis has important research value in theory and engineering. The main innovation points of this thesis are as follows.1. Designed and implemented a multi-layer, non-blocking ring No C architecture,and evaluated its performance.Multi-layer links achieve high link utilization and avoid protocol-level deadlock.The design of non-blocking leverages bufferless router to reduce hardware overheads.We also propose a scalable global signal control mechanism to eliminate the starvation and avoid the loss of packets. Compared with the conventional ring network composed of Dateline routers(DRing) and Intel Nehalem-EX ring network(NRing), our design achieves 69.4% and 12.3% performance improvements, respectively. Compared with DRing, it also reduces a large amount of hardware overheads, While the hardware overheads is similar with NRing.2. Designed and implemented a multi-layer, non-blocking hierarchical ring No C architecture.We propose a multi-layer, non-blocking hierarchical ring No C architecture. It holds the advantage of multi-layer and non-blocking ring. According to the traffic on rings,we leverage bidirectional multi-layer links on rings to reduce the number of node hops.The intermedia buffers between different rings leverage VC allocation scheme, which balances the traffic of packets between different local rings, and consumes small amount of hardware overheads. On the ejection part, we leverage Bouncing scheme. The local control scheme further reduces the global overheads.In summary, this thesis aims to the goal of high performance and low hardware overheads. We design and implement a ring No C structure and evaluate its performance based on a current multi-core DSP. We also design a hierarchical ring No C structure for next generation many-core micro-processors.