Heterogeneous Multi-core Structure On The Lower Ring Network Interconnection System Design And Implementation

As the further improvement and development of the design technology of VLSI and ULSI, the extensive use of Soc system structure encounter some problems as follow: transmission burden, clock synchronization and bus delay. Network on Chip(NoC) which is the newly born system interconnection architecture of multi-core age. NoC aiming at the features of multiple processing core, it adopting multi point communication mode and part clock synchronization technology to do data transmission which based on virtual circuit and packet switching, and changing the nowadays NoC system architecture in a quiet way.The thesis studied the present NoC basic architecture and the features and differences with on-chip bus architecture, introducing modified network on-chip interconnection plan from the research institutes in recent years. According to the design features of FPGA and the different emphasis of functions in the plans, we chose ring interconnection technology and shared cache mechanism, analyzed the possibility of the integrating of these two technology,the influence of heterogeneous computing, the throughput rate of the parallel data and some share problems. More over, we put forward a model, which based on the center of a parallel-accessible multiport shared memory, it is named as Ring-Bus Network on Chip (RBNoC).The thesis apply the EDA tools from Altera company and the Verilog Hard Design Language to design and simulate the communication node, network interface and Cache structure, make use of Quartus II8.0to synthesize,wired and simulated. At last, we download it to the Altera EP2C35F672C6FPGA chip on the DE2mainboard. The system can worked at the clock frequency of50MHz normally, and pass the test of basic write or read transmission.The testing results show that the function of system can meet the basic requirements of the heterogeneous multi-core processing unit to access data, from the aspect of routing complexity and data channel utilization rate, compared to the traditional NoC packet store and forward method, it has some complementary performance, and the parallel data access parameter is better than the traditional interconnection structure. The thesis will provide a support for further optimization design and applied research.