Research On Energy Efficiency Optimization Of Superscalar Processor

Modern processors have exploited very high instruction-level parallelism,including a series of techniques of static and dynamic instruction scheduling.They use technologies such as dynamic branch prediction and multi-issue to exploit high performance for modern processors.However,the developed high instruction-level parallelism also means that more hardware overhead and complex control logic are required to support it.But,as transistor leakage problems become more prominent,cooling problem caused by complex processor circuits has become an important factor limiting the further development of modern processors.Since then,Moore's Law and Denard Scaling Law,leading the computer industry,have gradually become less applicable.Energy efficiency optimization is an urgent task.In view of the above problem,this paper presents a Trace-based fine-grained superscalar pipeline power model.We add Trace Cache to the scalar pipeline and use Trace Cache to cache the sequence of instructions that we executed.When the instruction of the same address is fetched again,the subsequent instruction sequence is fetched directly from the Trace Cache and sent to the pipeline for execution without going through all the pipeline stages.Thus This can reduce the power consumption of the front-end of pipeline.The fine-grained superscalar pipeline power model proposed in this paper has three modes: OoO mode,OoOT mode and OoOR mode.The OoO mode is the mainstream superscalar out-of-order pipeline mode in these years,which has high pipeline performance and high power consumption.The OoOT mode adds Trace Cache mechanism into the OoO mode,which has a substantial reduction of power consumption without much affect on program performance.At last,we found that some programs themselves have a low level of instruction-level parallelism,and scoreboard algorithm lacks significant performance improvement in these programs.So we eliminate the scoreboard mechanism in OoOT mode and drastically reduce pipeline power consumption which we call OoOR mode.For different program characteristics and processor requirements,the user can adjust different modes to achieve a balance between performance and power consumption.We implemented the three modes proposed in this paper by the Gem5 simulator and performed performance tests using SPEC CPU2006 benchmarks.And McPAT was used to simulate power consumption.The experimental results show that the performance of OoOT mode is similar to that of OoO mode(with an average performance loss of3.6% while some programs show better performance in OoOT mode),while the average power consumption is reduced by nearly 8%.Compared with OoO mode,OoOR mode has a 29% lower performance and up to 58% reduction of power consumption(25% on average),but there also exist some programs which got a win-win situation in performance improvement and power consumption reduction in OoOR mode.At the same time,we tested the performance and power consumption of the three modes at different frequencies.The experimental results show that at different frequencies,the three modes show similar trends in performance and power consumption.Comparing the values of performance and power consumption at different frequencies,the performance and power consumption of different frequencies have different ranges,and the adjustment granularity of the three modes is smaller than that of different frequencies.Therefore,the experimental results show that the fine-grained superscalar pipeline power model proposed in this paper can complement the DVFS technology and adjust the program performance and power consumption in different granularity.