Instruction-level Parallelism To Develop Key Technologies To Achieve

In twenty years,the performance of microprocessor has reached very high,but new applications need more and more computing power. Nowadays,all of the microprocessor designs are based on the super-scalar technology,which has little room for improving performance more. In the near future,the architecture and organization of microprocessor will change greatly. It's the time to research new architecture for microprocessor design. This kind of researching work is very hot and important.One of the key elements to achieving higher performance in microprocessors is executing more instructions per cycle. However,dependencies among instructions,varying latencies of certain instructions,and execution resources constraints,limit this parallelism considerably. In order to exploit instruction level parallelism,processor should employ data dependence analysis to identify independent instructions that can execute in parallel.There are two types of data dependencies between instructions,register and memory dependencies. In both cases we can derive data dependences from reaching definitions and uses information obtained by data flow analysis. At schedule time true register dependencies are known,so register analysis does not involve any complication. But for memory dependencies we have to deal with the problem of aliasing (addresses are computed during execution).In this paper we propose a new simple approach for analyzing data dependence on DLX code using register queues. For each register we create a queue and the index of queue item means a function of executing time. The item in the queue is either null or an instruction whose operand is kept in this register. If one item stands for an instruction,its index has some relation with its earliest execution time.We also discuss a new approach for solving the problem of memory dependencies. Our analysis mainly concerns the determination of memory address. We use an address symbolic value propagation algorithm to derive possible address set that might be accessed by a memory instruction. Simulation results show that this two methods can detect data dependence not only exactly but also efficiently.