The Design And Verification Of Semaphore Part And Programmable Synchronous Memory Controller For M-DSP

With the development of the architecture of multi_core DSP, the demand of communication between cores becomes more and more strict. Shared Memory(SM) is a major method to solve this problem. As one of the critical technology of SM, synchronization access affects the efficiency of coherence about SM seriously. With the improvement of DSP's performance, DSP can process more data, there is an urgent need of a stable and reliable external memory interface to connect external memory.M-DSP is a new high-performance 32-bit floating/fixed point multi_core DSP chip developed by our school independently. The features and implementation of mainstream DSP's synchronization operations in shared memory were studied and an efficient Semaphore part containing 64 semaphores was designed and implemented based on the design requirement of M-DSP. Two kinds of requests were proposed according to different synchronous mode in different systems: interruption mode and polling mode. Direct request is a polling mode, and interruption mode contains indirect and query requests. The interruption mode was implemented by request queue, based on which the detection of error condition was monitored. A buffer with separate read and write commands and write data for read commands without write data was designed, which reduces invalid flip of data buffer and power loss caused by memory flip.To support multiple types of synchronous SRAMs, such as ZBT SRAM SBSRAM, A programmable synchronous static memory controller was designed and implemented. A variety of synchronous SRAMs can connect M-DSP simultaneously through this controller. The core of the controller is the FSM, which ensures the read and write date on shared data bus do not conflict by precisely control the commands with flow-control path. The data throughput is improved by optimizing idle clocks in the conversion between reading and writing.At last, the simulation and verification of of the two parts were completed by using NC_verilog. Asynchronous signal level and instruction code stimulus were developed to verify the design in module level part level and system level by using coverage-driven verification method. The results of verification show that the design meet the function requirement of the object.