Design And Implementation Of Usb 2.0 Ip Core In General Programmable Interface And Multi-bus Interface (gpmb)

The general purpose I/O and MuiltiBus(GPMB) is one of the main modules in the USB2.0 IP Core. GPMB module provides the 32-bit bus between USB2.0 IP Core and peripheral. The bus is programable.at this rate the user can program the MCU firmware to configure the correlative registers before using the bus. The user can also change the bus channel in the GPMB when the data of different type is to be transfered. In conclusion, GPMB module provides the communication channel between USB2.0 IP Core and peripheral. There is a Flash Controller in the GPMB module, and then the USB2.0 IP Core can be used to develop the device containning Flash.This thesis consists of the designing ,implementing and testing of a GPMB module. First,it briefly introduces the USB2.0 protocol,Flash memory related knowledges and the whole hardware design of USB2.0 IP core.Then it focuses on the design and implementation of the GPMB module, including the Flash Controller. In the end,it describes the unit test and system test procedure of the GPMB.GPMB is described by circuit diagram during the design phase, but is implemented by the Verilog HDL. In the unit test phase, the testbench simulates reading or writing registers by the MCU, then we can analyse the output waveform. In virtue of Sumsung's Flash memory model, the Flash controller is tested during the unit test phase.The system test of the GPMB is taken with the demo board. The GPMB module in USB2.0 IP Core has achieved the goal that we drew at the beginning. It provides preliminary study for the similar IP Core.