Research On Key Issueses Of Programmable Logic Cores

Programmable Logic Core (PLC) is a small-scale field-programmable gate array (FPGA). Embedding PLC into integrated circuit will benefit many fields such as shortening time-to-market, reducing development risk and prolonging the life cycle of product.The research topic is from the National High Technology Research Development Program (863 Program) project "Programmable logic core design and CAD software development" as well as the UESTC(University of Electronic Science and Technology) Key Youth Fund project"research on key technologies for SOPC ".According to the programmable times, programmable logic IP cores consists of MTP (Multiple Times Programmable) and OTP (One Time Programmable) IP cores. In recent years, Wilton and his team from Columbia University introduced the "soft core" concept to tackle the restrictions in the usage of "hard core". Although Flexible and easy to use“soft core”has two shortcomings. First, it is not compatible with the traditional two-way FPGA routing structure, which leads to a series of problems, such as inflexible wiring, and additional routing resources are required; not able to support sequential logic with feedback; the widely used CAD algorithms and popular tools of FPGA cannot be directly applied to "soft core", etc. Second, too large area. The area of“soft core”is 6 times larger than the area of "hard core". This dissertation article focuses on the main factors leading to the defects by analyzing the soft core design process. And based on this analysis, proposed a new design method, namely, "design method based on standard cell library and structure description”is proposed. The method uses a structured way of hardware description, and basic units from the standard library can be applied directly to form the basic programmable logic unit, and the whole programmable IP core is easily constituted by the basic units taking advantage of the symmetry and regularity of programmable logic core structure. Programmable logic IP cores designed according to this method are still flexible and easy to use, besides, 50% area is saved compared with Wilton’s“soft core”. This method is also silicon verified. According to the literature author can reach, this design method is introduced for the first time.In the field of OTP Programmable logic IP cores, anti-fuse programmable logic core is irreplaceable in high reliability, anti-irradiation, and other special applications, the application of its kind is desperately in need. For it’s compatible with CMOS process, anti-fuse programmable logic core based on MOS control gate oxide breakdown technology is easily integrated with SOC , but the resistance is large and widely dispersed after the breakdown of MOS-type anti-fuse, which is difficult to use directly in the programmable logic core as programming-bitt. This paper presents a new programming-bit architecture, and a Chinese invention patent ("the common bits used in the circuit and FPGA programming methods", application number: 201110112925.1) is applied. The programming-bit consists of two anti-fuse and one select CMOS device, it can provide high and low voltage levels to control the status of the certain nodes in the circuits, and the resistance character of anti-fuse itself can be completely ignored. So the MOS anti-fuse can be easily used in the programmable logic core as a programming-bit. On this basis, we design an anti-fuse programmable logic IP core, which has been silicon verified.The verification and development of Programmable logic core are heavily relied on supporting CAD software systems, but the programmable logic core designed according to this paper is not compatible with commercial FPGA structurally, so there is no software available now. This paper follow the strategy of "integrate and improve existing tools module in industry and academia, and custom design part of the module", developed two complete sets of CAD software systems to support the programmable logic core research of both MTP and OTP IP cores. This software system has been successfully applied to experimental verification of programmable logic core designed in this dissertation. In this project, the author innovatively modified the open-source isolated island structure FPGA place and route tool VPR developed by University of Toronto into an anti-fuse programmable logic core which support row-based routing.