Research Of One Type Of New DrMOS With Flip Chip & Stacked Die

A new type of package of DrMOS,QFN3.5x5 was developed and researched with flip-chip & stacked die technologies.In the new package, two MOSFET die and one IC die are integrated into the power device module, which achieves the high efficiency and low occupied PCB area. The process is categorized by wafer level process and assembly process. Wafer level process includes Ni Au plating on the wafer top side, then flux dipping and ball drop, flux cleaning. After that, wafer molding on the wafer top side & post mold cure, grinding top side until the solder ball electrical anode is exposed. Then grinding wafer back side, etching, metallization by vaporization TiNiAg metal. These are the whole wafer pre-treatment process. Based the package design structure, structure stress was simulated with the software Abaqus. In the simulation, different design was compared and come out the optimized design.Assembly process includes flip chip process, clip bond process, stacked die process, wire bond process, etc. Dispensing the solder paste to the lead frame pad and attach the high-side die to the lead frame with solder paste by flip chip methodology is the first assembly process, flip chip. Clip bond process bonds the low side die and clip individually to the lead frame pad and low side MOSFET drain & high side MOSFET source with solder paste, which is as same as the solder paste used in the flip chip die bonding. One IC chip is bonded on the clip by non-conductive epoxy after the semi-finished-product is cleaned to remove the residued flux. Wire bond process follows the IC bonding step to connect the internal bonding pad and out function leads.The solder ball drop process, wafer molding process, flip chip process, clip bond process and the flux clean process were studied. The effects of the parameters, the design of dispenser heads and the type of clean chemical were studied in these processes. The parameters were optimized according to the experiments and the results were verified by low side chip bonding, clip bonding, wire bonding processes. A new type of power management device module(DrMOS) was developed with above processes. The thermal performance was studied by the professional FAE simulation software Flotherm and addressed the factors which affected the package & chip thermal performance, and worked out the possible improvement measurement. The stress of package structure was analyzed to compare the different design candidates, and verified the selected design if it's the most optimized one.The study of low side chip flip chip bonding process shows that the hole diameter and the insert height of the dispenser heads is very sensitive to the stable dispensing. The slot was designed on the lead frame to lock the clip in the high side die bonding to prevent the clip rotation. The half etching on the bottom of clip and through slot were designed to decrease the structure stress. The popular clean chemical was studied as well as the different clean parameters to check the effects on the backward wire bonding process.The package thermal performance was studied and the via amount on the applied PCB beneath the package has significant effects on the package board & chip junction temperature, more via helped to decrease the package board and chip junction temperature.According to temperature distribution and strain measurement data of the real products when power was loaded in the part, all of data are within the tolerance of design and mass production. That shows the new product development met our target and made the achievement.