Planar source pocket (PSP) tunnel MOSFET: Potential device solution for low power applications and improving tunneling MOSFET performance

As MOSFET is scaled below 90nm, many daunting challenges arise. Short channel effects (DIBL and VTH roll-off), off-state leakage, parasitic capacitance and resistance severely limit the performance of these transistors. Moreover as the device dimensions are being scaled down into the nanometer regime, power dissipation is becoming a principal concern. Supply voltage scaling constraints and the diffusion limit of 60mv/dec on the sub-threshold swing (SS) lead to reduced ION/IOFF and high I OFF. This leads to higher active power dissipation and sub-threshold power consumption. To provide for a given overdrive and control power dissipation, lower threshold voltage is required while maintaining a low IOFF. This points to the pressing need for devices with steep (< 60mv/dec) sub-threshold behavior. New device innovations are essential to overcome these challenges. In recent years, research in novel devices (tunneling FETs, IMOS [1], [2]) for possible solutions towards providing steep sub-threshold behavior and improved ION at lower operating voltages has gained a lot of momentum. Most of the tunneling devices investigated have the configuration of gate controlled reverse biased p-i-n diodes ([3] - [8]]. Some of these devices have been shown to exhibit <60mv/dec SS albeit at very low current levels (∼pA range) after which the swing degrades rapidly. The on-current is also several magnitudes lower than conventional FETs. In addition, they suffer from ambipolar behavior. In this work, we propose and investigate the concept of a novel Planar Source Pocket Silicon Tunnel n-MOSFET based on the principle of band-to-band tunneling. The Planar Source Pocket (SP) Tunnel n-FET has the potential to improve source tunneling, achieve steep sub-threshold swing and improved ION as compared to the p-i-n device. Such a device can potentially overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The physics and design of the planar SP Si n-TFET were examined extensively using process and device simulations which show that steep sub-threshold characteristics (SS ∼5-10mv/dec over 4 current orders from 0.1pA/microm to 1nA/microm) can be achieved for sufficiently abrupt source tunneling junction profiles (≤2-3nm/dec). Devices with source side tunneling junctions were fabricated using ion implantation on bulk and SOI substrates using spike and conventional anneal and the experimental data is presented. It is found that SP n-TFETs with shallow source p+-n pocket (which is fully depleted) tunneling junctions provide a higher I ON and improved SS than their p-i-n counterparts. At the same time, further improvements in device performance can be achieved using multiple strategies (novel dopant techniques, SiGe/Ge tunneling source etc) to make the SP n-TFET a promising alternative to conventional MOSFET, especially for low power applications.