Impurities Segregated Simulation Research Of The Field Effect Transistor

As feature size of the integrated circuit(IC) devices keeps scaling down, the source/drain(S/D) depth becomes shallower and shallower, and the S/D pn junction of conventional device leads to a huge parasitic series and contact resistance, at the same time devices also meet challenges in fabricating shallow junctions. Schottky barrier MOSFET(SBFET) has attracted a lot of attention since it naturally has the advantages, that are low S/D parasitic resistance and easy realization of shallow junction. However, the Schottky barrier between the metallic S/D and channel area is limited by S/D material and contact condition will impact the on-state current badly. Therefore, the dopant-segregation technique has been introduced to lower the barrier height and increase the current, by forming a heavily doped thin layer between the S/D and the substrate/channel. The thesis will investigate the working principle and estimate the application prospect of dopant-segregated Schottky Barrier MOSFET (DS-SBFET) by device simulation.The device simulator Apsys, which is the product of Crosslight Company, is thoroughly introduced. The tunneling model of Apsys is verified by giving a simple Schottky contact simulation.The theoretical analysis and simulation investigation are employed on the dopant-segregated Schottky contact which also named Shannon contact. We use the Apsys to simulate the contact, and then extract the effect SBH with the Ⅰ-Ⅴ simulation data..The result reveals that by adjusting the thickness (thinner than10nm) and doping concentration in a certain range will lead to a different effective SBH. As to the metal/p+-n structure, with a4.7eV work function of the metal and lel5cm-3doping concentration of the Si, it got effective SBH(electron) varies from0.66eV to0.93eV. As to the metal/n+-n structure, under a certain range of settings, it becomes to an ohmic contact with ultra low effective SBH.N type MOSFETs are built under45nm and65nm process generations by referring to reports, and simulation results are rather comparable with the reference. The origin of DS-SBFET gets a high on-current is revealed via comparing the simulation result of DS-SBFET and conventional MOSFET:DS-SBFET lacks of the S/D extension area leadsto a lower S/D series parasitic resistance, and the thin layer with heavy doping influences the carrier distribution in the channel area lowers the threshold voltage of the device. And it is believed that the DS-SBFET with a not-fully-depleted thin layer had no difference with the conventional MOSFET without S/D extension area, and a DS-SBFET with fully-depleted thin layer would not get a high on-state current as reported. At the same time, both of them will suffer a severe short channel effect.Finally, the thesis proposes an asymmetric DS-SBFET which can suppress the short channel effect and enhance the Ion/Ioff ration, but the performance of DS-SBFET is still not as good as the conventional device. The conclusion is that DS-SBFET cannot be used to replace the conventional MOSFET with S/D extension in the VLSI under65nm,45nm or smaller scale manufacture technology node.