The ASIC Design Of Reconfigurable 2D Floating-point FFT8192 Processor

Fast Fourier Transform(FFT)is widely used in the digital signal processing.2D FFT transform is more widely used on the synthetic aperture radar, medical imaging systems and other system applications. The amount of data to be processed is increasing and the accuracy of the data processing requirements continue to increase. With level of the integrated circuit increasing,developing a large number of points can be configured for high-precision 1D/2D FFT processor is necessary.This design achieves a strong FFT processor by ASIC, named FFT8192 ASIC.The design of the FFT8192 processor has configurable function,it can achieve 1D FFT/IFFT continuously variable sequence transformation and also can achieve continuously variable frame 2D FFT/IFFT transform.Specific design work:completing front-end logic design and verifaction on Modelsim, comparing the result of simulation on hardware and software and getting computational accuracy and processing speed of test. And we employed in SMIC 0.18 ? m technology 100 Mhz clock frequency,we complete logic synthesis, design for testability, formal verification, static timing analysis, layout, clock tree synthesis and other physical design and DRC, LVS,ERC and other physical verification, and ultimately through the static timing analysis, post simulation.If the logic design and timing meet requirement,we submit final layout and tape-out and package and test?In this paper, the design of the ASIC FFT 2D FFT8192 transform uses the ranks of the decomposition algorithm.We repeat use one dimensional FFT kernel with less resource consumption.In the ranks of the transpose operation, we put forward a way of operation of transpose rows, it can realize the transpose of the SDRAM read and write is almost not affected by row activation and precharge operation.This design provided synchronous serial and I2 C bus interface. It can reduce the number of chips port,as a commoninterface,other master chip can easily configure parameters. ASIC FFT8192 is embedded in a digital phase locked loop,It used as frequency multiplier low jitter clock internally generated, a small phase difference.This design of phase-locked ring control module uses occupancy less port UART receive PLL configuration parameters,Phase locked loop control module uses continuous start mode auto start PLL; when the external parameter changes, PLL can immediately be restarted or changing the work mode.Finally we achieve this design and its bare area is 9528 um x 9528 um, BGA area is15mmX15 mm,on the ATE equipment testing PAD power consumption is 90.255 mW, core power consumption is 889.452 mW, analog power consumption is 69.822 mW, the total power consumption is 1049.529 mW.