Research Of The Floating-point FFT Accelerating System

A novel reconfigurable floating-point FFT accelerator for accelerating scientific computing is proposed in this paper. It consists of two parts:(1) reconfigurable floating-point FFT processor (2) FPGA hardware systems.This paper focuses on the decomposition method and hardware implementation of the FFT architecture. The Radix-2/22/23/24 balanced binary tree decomposition algorithm is used to reduce the numbers of common complex multipliers and the twiddle factors. The improved SDF structure with multiple pipeline stages can speed up the FFT operation. To deal with access confliction to delay unit, the proposed method is adopted for temporary data storage. The architecture based on the constant multiplier, reconfigurable multiple constant multiplier and multiple constant multiplier optimizates the area. In addition, simple and reliable transport protocol is proposed in this paper, based on 10G Ethernet hardware platform. And high-speed FPGA-based DDR3 controller is designed. It can support the high-speed, reliable and large data access in the real-time digital signal processing.In this paper, the proposed accelerator has been verified on a XC6VSX475T FPGA device with the working frequency at 181MHz. The synthesize frequency is 258MHz. It can support 32 to 131072 points double-precision FFT calculation. And the occupition of the LUT resources is 35%. The calculation error is 3.68* 10-16. It is more than seven times faster than FFTW 3.3.3 running on an IBM server based on 16-core 1862.059 MHz CPU and 64 GB memory.