The ASIC Design Of Reconfigurable Floating-point FFT Processor

FFT is one of processing methods that widely used in digital signal processing, such as image/audio processing, wireless communication and radar imaging system, to realize signal processing and transmission in frequency domain. With the enhancement of the application system requirement and the development of integrated circuits, larger length points and higher precision computation become more and more urgent for the system.The target application field of this design is on-satellite radar imaging system, and on the basis of the analysis on different FFT algorithm and VLSI architecture, this paper presents a reconfigurable R2/22SDF pipeline algorithm and architecture, including RTL coding, functional simulation and logic synthesis done. Single-path delay feedback pipeline can improve the processing speed and lower the restriction of the external memory data bandwidth with favorable chip pins. Radix-4algorithm with less complex multiplication and multiplication times is proved to be more effective than Radix-8. Every two kind of points shares a common data input port and every FIFO memory has two working mode:full-depth and half-depth, this reduces about half use of the complex multiplication and rotation factor addressing circuit and storage.The rotation factor feature on different stages is studied, and the lower cost addressing circuit is proposed, and the design uses a new comprehensive analysis method which can better balance complex multiplication and rotation factor addressing/storage resource cost.In order to reduce the workload of the external master device and sequential addresses is needed for burst read/write operation, a new bit-reversal module with high data schedule strategy is designed, which based on two N/2depth single port memories. This new bit-reversal design reduces the area cost significantly compared with traditional methods which based on one N depth dual port memory or two N depth single port memories.This chip can calculate26～213length FFT/IFFT, with natural order input and output, and integer/floating-point data format to choose. Hanming code/decode is used to correct single bit conversion and report two bits conversion case, because the space environment can trigger single event upset in the electronic device.The circuit also has synchronous reset and pipeline stop function.The data output delay is about2N cycle, and it can have1data/cycle data input/output ability under sequential processing. The chip is synthesized with SMIC0.18μm process under100MHz clock, the equivalent gates is about1093K, power dissipation of134mW, with160Kbytes RASP/RFSP and16Kbytes ROM on chip, and total area cost is14.55mm2.