Design And Implementation Of High Speed Digital I/O System Based On FPGA

With the rapid development of aviation and aerospace technology, the performance of embedded electronic system is becoming more and more complex, the amount of data transmission is increasing day by day, and the data transmission rate is increasing. As a result, the ground test system of aviation equipment is gradually tending to the development direction of automation, high speed and multi function. In view of this trend, this paper designs a kind of high speed digital I/O system based on FPGA, which is designed by adopting the key technologies such as high speed buffer,PCIE bus and dynamic reconfiguration, implement the real-time data transmission with the host computer, and realize the dynamic reconfiguration of various functions of the system, so as to achieve the universal test equipment.Firstly,around high-speed digital I/O system in the field test research background and development status were analyzed in detail, And according to the current development bottleneck of the digital I/O field, the key role of the high speed digital I/O system is deeply studied, such as the high-speed cache, the PCIE bus, the dynamic reconfiguration and so on,and proposes a method based on multi functional dynamic reconfiguration of high-speed digital I / O system design case.Complete the design and selection of the various technical difficulties.Secondly, the technical difficulties one by one to carry out detailed logical design and timing analysis:1. in the cache module,the design method of table tennis table based on SDRAM DDR2 chip is mainly used,Improved the original dual channel cache method.And in order to increase the data transmission rate, the method of static timing analysis is used to analyze the timing slack and the maximum operating frequency,and the timing violation phenomena were improved by pipelining and synchronous drive technology,the time achieved the best condition,make the timing effect to achieve the best state.2. in the PCIE bus module,the based on Xilinx PCIe hardcore are used in user's logic design and implementation,which mainly includes the sending, receiving,instruction resolution module.Because the project needs to be involved in the dynamic reconfiguration of a variety of system functions, the instruction resolution module uses the BAR0 space which is mapped with the host computer to carry on the instruction transmission.According to the time sequence of DMA, the timing analysis of each function module is carried out, which verifies the correctness of the data exchange of PCIE bus.3. in the dynamic reconfiguration module,For data rate reconfiguration, this paper uses PLL(Analog) +DCM(digital) design method to achieve,which PLL module used to produce low jitter of high quality internal clock signal, the DCM module used to generate configurable high accuracy interface clock signal.Aiming at the logical level reconfiguration, this paper uses two design methods, which are the overall reconfiguration of the FPGA and the reconfiguration of the external hardware circuit,and their respective advantages and disadvantages are compared andanalyzed.For the transmission mode reconfiguration, this paper uses the design method of local reconfiguration, and realizes the dynamic management of I/O resources in FPGA.Finally, according to the requirements of each index, the corresponding test environment is set up. After the system debugging, the system completes the high-speed data transmission, at the same time, it also realizes the dynamic switching of 32 channels data transmission rate per channel dynamic choice between the 10 MHz to 100 MHz, Automatic configuration of logic level in 3.3V, 2.5V and 1.8V,data transmission between 32 common I / O and 1 high speed I / O dynamic switching,All the indexes meet the design requirements.