Study Of Dynamic Power_adaptive Technology Based On Hardware

The dynamic power_adaptive technique has broken the tradition of the static architecture design in the microprocessor field. It offers a power_adaptive mechanism for key hardware resource on the chip. By analyzing the demand of applications through software, the dynamic power_adaptive technique can offer hint information to hardware, make reconfigurations of the hardware sources according to the change of the demand, and close unnecessary or invalid redundant resources. On the premise of guaranteeing performance, the dynamic power_adaptive technique always serves the present application with the most suitable resource, so as to achieve the goal of saving consumption.This paper has proposed a kind of dynamic power_adaptive technique purely based on hardware, which need not software to provide the hint information. By setting up the fixed time slot, the hardware collects the procedure execution information of present time slot totally by itself, and determines the best configuration of hardware resources of next time slot at the end of the present time slot, so as to save the consumption.The paper designs and implements three kinds of dynamic power_adaptive hardware structures: the two level adaptive cache of selective ways, the chaining issue queue based on CAM/RAM and the method of closing pipeline stages based on EPIC (Explicitly Parallel Instruction Computing). By setting up the consumption estimate models of them, we use the simulator to make performance analysis and consumption simulation. The simulation result shows: Individual part consumption of cache optimization proportion is up to 60%- 70%, individual part consumption of issue queue optimization proportion is up to about 30%. The result of the method of closing pipeline stages based on EPIC prove invalid consumption proportion which can save in the EPIC processor is nearly 90%. But from the simulation data we can find out consumption optimization complies with Amdahl law too. Only optimizing a part is not enough, no matter cache but also issue queue, the optimization proportion of the total consumption of the processor is under 10% basically.Because we have not offered the corresponding mechanism to monitor performance in the course of consumption simulation, so performance is lost partially. In addition, the simulation result shows the lost performance of most benchmarks is generally about 5%, and that of minority is less than 2%. If really implementing this kind of technology on the processor, we must offer the corresponding mechanism to monitor performance and guarantee that system does not suffer a large performance loss.In addition, the paper discusses some key mechanisms which are indispensable to implement a dynamic power_adaptive system, and sets up two models of dynamic power_adaptive system with the smart compiler and without the smart compiler, but not make performance analysis and consumption simulation.