The Design Of Buffer Management Unit In Gigabit Network Protocol Processor

With the rapid development of network, high-speed transmission and information security of network data have become a part of the national Internet healthy and rapid development strategy. Along with 100 Gbps backbone deployment is complete, the network protocol processor by the combined way of hard and soft gradually replace traditional network data processing program to meet the demand of the enterprise network processing bandwidth in present stage. The efficient processing and fast forwarding of various business packets require the network protocol processor with higher buffer management performance. Buffer management unit realized by hardware circuit has become the indispensable part of network protocol processor with high performance, playing a very important research significance.Based on the national nuclear high base project "Gigabit Network Protocol Processor (NP)", the thesis propose the combined scheme of the address management way based on two stages FIFO and partition storage management way, and implement the circuit design of buffer management unit (BMU). BMU is divided into the management channel of buffer identity (BID) and the management channel of buffer data. The two channels are independent of each other, sharing with a AXI Master interface, to access the off-chip as high as 1GB buffer space in the burst way. BMU adopts the arbitration algorithm of dynamic weighted round robin (DWRR) to realize the shared buffer management functions with multi-interface. According to the scheme, the thesis makes module partition and structure analysis, using Verilog language to complete the Register Transfer Level (RTL) design.Firstly, the thesis set up a functional verification platform, using VCS Synopsys and Verdi simulation tools for functional simulation. Secondly, the thesis maked the circuit synthesis using DC synthesis tools with SMIC 65nm technology library. Finally, the thesis verified the function of the circuit in Xilinx Virtex 6 development board. The results show that the circuit can achieve the efficient management of BID, the fast storage and forwarding of the buffer data. And the circuit can work under the clock of 400MHz. The deisgn can be widely used in a variety of high performance network protocol processor, and it has important engineering application significance.