Wide Range Voltage Scaling Optimization On SoC

With the sharp development of IC and MT (Mobile Termination), the requirement of performance in the generation of Multi-Media leads to huge power consumption. Power consumption is a major concern in IC design flow because of the battery life and the demand of UE (user experience). Dynamic Voltage and Frequency Scaling (DVFS) technology and Adaptive Voltage Scaling (AVS) technology have been used widely. However, there is relatively a lot of time cost in AVS implementation, and the power saving yield of single implementation of DVFS or AVS is relatively limited.A system of combined regulation is chosen and a verification circuit is also designed finally in this thesis, in which the DVFS technology can be implemented to realize fast power supply switch. Meanwhile, a combination of DVFS and AVS can be used to release timing margin on two level. (1)Coarse regulation (DVFS) first can be realized by basing on soft ware schedule and hard ware implement. (2)The fine regulation (AVS) is realized by detecting timing margin of replica critical paths, which can track critical paths according to post-silicon self-regulation and double-cell replacement. DVFS module is used to scale voltage and frequency fast while AVS module is used to adjust two voltage rails according to the PVT condition slowly respectively.In this thesis, SMIC 40nm process is applied to complete the whole design and a small SoC has been built to verification the combined system. The whole chip can run in two different patterns, including 1.1V/250MHz and 0.6V/20MHz. COSIM HSIM-VCS platform has been built to simulate the whole chip. Verification through COSIM platform depicts that in condition of standard voltage of 1.1V, voltage can decline to 0.84V in typical case (TT corner、25 ℃), and power consumption can save 28.1% in contrast to initial case (TT corner、1.1 V、25℃). In low voltage of 0.6V, it can get more than 24.3% power yield in typical case (TT corner、0.6V、25℃). So, by this system, power consumption can be saved efficiently. Also, the power selector circuit is implemented to get transition speed up to 600ns, and the transition efficiency is about 80%, which realizes fast switch, And AVS module cost 2% areas totally, which has little area cost.