Performance And Power Prediction Models On Multi-core Processors For DVFS

The developing of the semiconductor technique makes the amount of the on chip resources increases rapidly. Compared with the single-core processor, multi-core processor could make better use of the on chip resources. Thus it develops very fast in the past ten years. However, as the failure of Dennard Scaling, power has become a first order concern on multi-core processor now.Dynamic Voltage and Frequency Scaling(DVFS) and Power Gating(PG) are employed on modern processors to scale their performance and power. DVFS changes the frequency and voltage of the cores, scaling performance and power simultaneously. PG cuts the power supply of the idle cores to reduce the power consumption. Usually it is used together with thread migration. These techniques are widely used in practical. In this dissertation we explore their relationships with the performance and power of modern processors. We proposed prediction models on commodity processors to expose these relationships and take Power Capping as an example of their usage. The contribution of this dissertation is as following.We propose LL-MAB, a performance prediction model across DVFS states. Starting from measurements taking at one DVFS state, LL-MAB could predict the program’s execution time at other DVFS states. LL-MAB is the first implementation of the Leading Loads method on commodity processors. It takes only two performance counters to get the computation time and the memory accessing time without data regression. We implement LL-MAB on 3 AMD processors, the accuracies of the performance predictions are between 94.7% to 97.3% across >2X frequency differences.We propose PPEP, a power prediction model across DVFS states. Starting from measurements taking at one DVFS state, PPEP could predict the power of the processor at other DVFS states. In PPEP, we build a temperature aware idle power estimation model and a performance counter based dynamic power estimation model. After that, based on two experimental observations about the relationship between DVFS states and perinstruction event counts, we connect the power estimation models with LL-MAB model to build PPEP model. Thus, PPEP could predict power and performance across DVFS states. We implement PPEP on AMD FX-8320 processor. The power prediction accuracy is 95.8% across all DVFS states pairs.We propose SCP, a performance prediction model for thread migration on Clustered Multi-Threading(CMT) processors. CMT architecture is employed in AMD Bulldozer, Piledriver, and Steamroller processors. Different with SMT processors, the hardware threads in CMT processors have more private resources such as integer unit and L1 data cache. Two hardware threads locates at one Compute Unit(CU) and share other resources such as floating-point unit, L2 Cache. Through thread migration between CUs we could change the threads co-running state between separated state and clustered state, which scales the performance and power of the processor. SCP could predict the performance impact of the thread migration. By SCP, starting from measurements to the threads before the migration, we can predict the performance of the threads after the migration.We implement SCP on AMD FX-8320 processor. The performance prediction accuracy is 93.5% when the thread co-running state changes from separated state to clustered state, and the performance prediction accuracy is 93.8% when the thread co-running state changes from clustered state to separated state.We propose PPEP-SCP, which is fused by PPEP and SCP, for CMT processors.PPEP-SCP could predict performance and power for the changes of DVFS state and thread co-running state. Using the IPC value predicted(across thread co-running states) from SCP and the power value predicted(across DVFS staets) from PPEP, PPEP-SCP could predict the power when DVFS states and thread co-running states all changes. However,this prediction is in coarse grain because we only use IPC to do the power prediction between thread co-running states. We use PPEP-SCP to build power capping strategy, using DVFS and thread migration to fit the power cap. Compared with PPEP strategy, PPEPSCP strategy could get even better effect because it uses both DVFS and PG technique.