Research On Low Power Low Noise Amplifier With Nanometer CMOS Technology For Wearable Smart Device

With a fast economic growth, the Internet and mobile Internet is also well popularized in the world. Based on this backgoundmore and more requirements are coming up to improvethe quality of people's life. Wearable devices combining kinds of application software will accelerate this intelligent life trend. So the market window of wearable devices has been opened widely.However, power consumption has always been a bottleneck for the restrict power consumption target in wearable devices. Power consumption is an important specification for the wearable device application scenario. To meet the power consumption challenges,a common low power wireless communication standards, the low-power consumption bluetooth standard is used for the wireless connection in wearable device. Under the background, the nanometer CMOS process is selected to fabricate the integrated circuits in wearable devices. So in nanometer CMOS technology a low noise amplifier will be the most key design for the wireless communication of smart wearable deviceThis thesis describe my work to realize a low power low noise amplifier designed in SMIC 55 nm CMOS technology which is compatible with the low energe bluetooth standard(BLE). This thesis is prepared in the structure of background introduction, LNA design theoretical analysis and specification definition, circuit scheme design and optimization, layout design and verification, testing and conclusion. A common source structure is selected for the low power low noise amplifier. A careful optimization is necessary for this LNA design to gain a good balance between the input impedance performance and noise performance while it is realized in 55nm CMOS technology. Meanwhile, to realize a high integeration scheme, the match network was fully integerated in LNA. So this LNA in 55nm CMOS technology is designed and optimized towards wearable decice applications.This design work are finised in the Cadence EDA environment. It includes the circuit design, corner simulation, layout design and verification, gds file preparation. After the MPW, the test results show that this design the low noise amplifier on the basis of the power supply voltage of 1.2 V, working in the 2.4 GHz frequency band, the input matching feature is good. The gain is 10 dB, the noise figure is 4 dB, input 1 db compression point is -3 dBm, and input third order intercept point is 7 dBm.This thesis gives a silicon proven low noise amplifier design from circuit analysis to die test. The test results show the design target is met.