A Method For Statistical Static Timing Analysis At Near-threshold Voltage

For all the time, decreasing the circuit working voltage is an effective way for low power design. However, with the voltage decreasing, the influence of local variation on the circuit's performance also increases. This makes the traditional static timing analysis method that based on corner estimates circuit's delay pessimistically, and no longer suits near-threshold voltage design. Usual statistical static timing analysis method assumes cells' delay as Gaussian distribution, which not accurately reflects the situation of near-threshold voltage. Therefore, a kind of efficient statistical static timing analysis method which supports the cells' delay for non-Gaussian distribution is needed.This thesis combines with cell characterization and timing path analysis, and presents a near-threshold voltage suitable statistical static timing analysis method. In the cell characterization part, the operation point algorithm is used to get discrete values of delay distribution, at the same time, due to the large amount of simulation and long runtime of the characterization, the inverse Gaussian distribution model is proposed to fit the delay distribution, in order to improve the algorithm. Theoretical analysis shows that the using of inverse Gaussian model can decrease the simulation to 1/12 of the original amount of simulation. In the timing path analysis part, the correlation between cells' delay is also considered to get paths' delay with operation point method. In this thesis, more than 95% of the non-critical paths is eliminated by combining methods with static timing analysis on data paths and statistical static timing analysis on clock paths, this greatly accelerates the timing closure of the circuits.Based on SMIC 40nm LP process platform, this method is tested and verified on benchmark circuits ISCAS89 and circuit Cortex-M3. The results show that, when error within 10%, cell characterization using inverse Gaussian model fitting method can reduce more than 85% of the runtime. In timing path analysis, when compares with Monte Carlo simulation results, the errors of 3a delay of circuits' random paths are within 10%.