| As mobile portable electronic products development and popularization, the limited battery capacity leads to energy supply tension of the equipment. In order to cater to the trend of IC development in the of low power consumption, the emergence of NTV(Near Threshold Voltage) technology makes it is possible for circuit to has higher energy efficiency. In this paper, a kind of fast adder with high energy efficiency under the NTV’s power supply is designed by the improvement of the XOR-XNOR unit, the sum unit and carry out unit based on the SMIC 65 nm process. The main work is as follows:1. The XOR-XNOR unit in the fast adder is designed. First of all, the traditional XOR-XNOR circuits are divided into three categories, i.e. weak current signal style, un-balanced output style and ratio logic style. At a low voltage supply, their performance deterioration is discussed respectively including a) wrong selection of high signal and low signal caused by incomplete output swing; b) the unwanted circuits glitch generated by asynchronous output; c) a dependent relationship between the transistor size adjustment and the circuit performance due to the existence of feedback structure. To ensure the circuit speed, a size-independence, balanced full output swing XOR-XNOR under the near threshold voltage supply is proposed.2. The sum unit in the fast adder is designed. In the design of sum unit, the problem of signal interference between modules is first analyzed. A signal isolatied circuit structure using the insulating properties of gate in CMOS is proposed to avoid the electrical signal interference caused by bi-directional conduction in pass transistors. Then, in order to solve signal contention in this isolated circuit, a size-cutting method is adoptet to improve sum unit speed.3. The carry out unit in the fast adder is designed. A rapid inverter is designed by increasing paths in the inverter’s pull-up network. By using the fast inverter, the carry out unit is improved to make it have full output swing and good dirve capability.4. The XOR-XNOR unit, sum unit and carry out unit in adder are verified by HSPICE based on the SMIC 65 nm CMOS technology. The results show that: 1) under the voltage of 0.3V to 1.2V, compared with traditional XOR-XNORs circuit, the improved XOR-XNOR unit has the fastest speed and the highest energy efficiency. And circuit speed is improved by 57%~98%, the energy efficiency is improved by 72%~2926% under the supply voltage of 0.4 V; 2) Under the supply voltage of 0.3V~1.2V range, the size-cutting method improved the performance of energy efficiency and speed of sum unit without affecting the circuit power consumption and area. Under the supply voltage of 0.4 V, the sum unit speed can be increased by 38%, the energy efficiency can be improved by 57%, and the power consumption influence can be neglected; 3) Under the voltage of 0.3V to 1.2V, the PMOS pull-up speed is improved. At a supply voltage of 0.4 V, compared with traditional circuit, the power consumption of proposed inverter is increased by only 2%, however, the carry out unit speed is increased by 54% and the energy efficiency is increased by 66%. 5 A high energy-efficicent and fast hybrid adder is designed by the optimization of XOR-XNOR cell, sum cell and carry out cell under the near threshold supply voltage. Based on SMIC 65 nm process, in the full range of of 0.3V to 1.2V, and under the condition of 121 inputing switching, the proposed adder’s performance is verified by HSPICE, and is compared with six conventional adders. The simulation results show that under a full supply voltage range, the proposed adder has rapidest speed and highest energy efficiency, also a complete output swing. When the supply voltage of 0.4V, the power comsuption is only 7.11×10-9W,which has a 2095.64 times reduction in the power than that at nominal voltage supply. Compared with conventional adders, the speed of propsed adder is increased by 35.7% to 54.7%, and the energy efficiency has a 53% to 139.7% promotion. |
PDF Full Text Request