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Implementation Of Software And Hardware Modules For The NP-based Multi-network Gateway

Posted on:2016-12-01Degree:MasterType:Thesis
Country:ChinaCandidate:H D ZhangFull Text:PDF
GTID:2348330488974143Subject:Engineering
Abstract/Summary:PDF Full Text Request
The change of customer's demand and the evolution of telecommunication, network and computer technologies result in the coexistence of various networks. We thus need a gateway to complete the conversion of different communication protocols and to implement the interconnection of different kinds of networks. With advantages of both general-purpose processors in excellent flexibility and application specific integrated circuit(ASIC) in high-speed hardware processing, network processor(NP) has become an important development platform for telecommunication equipment manufacturers to develop devices such as switches, routers and firewalls. The development platform based NP has such advantages as superior performance, programmability and reconfigurability. Based on Intel NP IXP2350 development platform, the multi-network gateway developed in this thesis could implement the interconnection of network interfaces of SDH, GE, V.35 and E1.Supported by the National High-Tech Development Project(863 Project), the test and simulation of the new generation of integrated satellite and terrestrial broadband communication networks, the implementation of software and hardware modules of multi-network gateway is completed on the basis of original work of the research group. A summary of researches on multi-network gateway in recent years is given. An introduction to the hardware architecture, software architecture and development environment of IXP2350 is presented with an emphasis on its inner structure of ME(Micro Engine). The hardware implementation of synchronous digital hierarchy(SDH) link based on PM5352 and SFP is described in detail. In the software aspect, the design and implementation of ME module, control module on XScale and human-machine interface on PC are completed. This thesis makes a detailed description of function allocation of MEs and threads within IXP2350. Implementation of data packet segmentation and reassembly as well as the flow measure and control is performed by programming. To realize flow measure and control, original instructions between control module on XScale and human-machine interface on PC are extended to the support for new instructions, which are added to the drivers and control application on XScale. Flow measure and control subwindows are also designed and added to original human-machine interface, and the software programming of background processing is completed.To validate the functions of the hardware and software modules mentioned above, tests based on both instrument Smart Bits 200 and IP video terminals are performed. Test results indicate that multi-gateway software modules mentioned above could perform the functions as designed, but SDH hardware module remains to be amended a little.
Keywords/Search Tags:Network Processor, IXP2350, multi-network interconnection, flow control
PDF Full Text Request
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