The Verification Of Video Image2D To3D Module Based On UVM

With the rapid development of technology and design capacities, in order to meetthe requirement for cost,functionality and power consumption of embedded systemmarket, Soc (System on-a-Chip) design technology has become a developmenttrend,which is pushing ahead, following the law that the Moore indicate,and hasconstantly expanded in the scale and function.As the increase of design size, theverification complexity rapidly rise,verification technology has lagged behind designand manufacturing capability,become the constraint bottleneck for the entiredevelopment of Soc technology, and obstacles to improve design productivity. Howto build a better and faster verification methodology to improve workautomation,reusability, flexibility and interoperability is the current issues that Socindustry concerns.UVM（Universal Verification Methodology） verification methodology is averification methodology with powerful function that was developed by manyindustry experts for their own research and development needs. It draws on theessence of many verification methodologies, including AVM（Advanced VerificationMethodology）、OVM（Open Verification Methodology） and VMM（VerificationMethodology Manual）,represents the latest progress of verification technology.Usingit can create powerful,flexible, reusable, interoperable verification platform and testprocess(test bench) components.Using UVM verification methodology to builtplatform greatly improves the efficiency of verification.Based on the analysis of video image2D to3D module,it researches and buildsthe block level verification environment by UVM verification methodology.Thispaper introduces the IP structure、function and interface of video image2D to3D indetail. Then based on UVM,a automated reusable tree structure platform is built withsystem verilog verification language.Based on this platform， it achievescomprehensive and high-efficient verification for video image2D to3D module by means of the combination of direct test and constraint random test。It reached93%code coverage and100%functional coverage within10days. It’s fully proved that,the UVM verification methodology has advantages in creating automation、reusable、efficient verification platform.