UART Environment Research And Development Based On UVM Architecture

As integrated circuits has entered the era of super-mole, the increasing complexity of the circuit, and therefore the difficulty of verification are also increasing, with the improvement of verification required, in the actual production, traditional direct verification has become increasingly difficult to meet design needs.In order to make our products more competitive, to obtain an advantageous position in the fierce competition in the market, to ensure proper function under the premise of improving code reuse rate, it has become an important method of verification cycles each company to shorten time to market cycle is shortened. To do this, we need to adopt a more effective verification methods, making verification more effective.In the market, driven by the increasing maturity of verification, only gradually into one.Has a high abstract UVM based verification of System Verilog, can improve code coverage generated by constrained random stimulus, such verification efficiency is greatly improved.In addition, since each module functions into UVM clear so that each module has a certain independence, so can good way to improve code reuse rate, which in the long run, greatly reducing the late development of new products to market. Due to the above advantages,UVM-based verification System Verilog has become more than the company verification IC mainstream, and still evolving.Verify that the object of this paper is TPCM project at Huahong Integrated Circuit Co., Ltd.participated in the placement of a MCU in use by a company independent designer designed UART modules. Through the basic components of the UVM verification platform,commonly used standard library study and research, and to analyze the function of each component modules to study the association and individual modules, use UVM verification methodology, build verification environment for UART, and for the latter system-level verification preparing improve code reuse rate, is the focus of this article. Through UART research and analysis, analysis of the characteristics of UART using UVM verification methodology characteristics generated by the corresponding module Sequence constrained random stimulus, monitoring Reference Model and the need to verify the output module through UART Monitor module, and by the Scoreboard module automatically compares the results. To verify the results to ensure the correctness of the final output waveform, the waveform selected representative analysis.Thanks to the guide of enterprise menter, the verification platform became ture ultimately,achieve reasonable value of coverage, making the task completed successfully.