The Design And Implementantion Of AMBA2.0 In MPEG2-DECODER IC And Co-Simulation

With the development of IC design technology and the increasing of the circuit density, especially System on Chip (SOC) design takes up a large amount of the design of digital chips, the conventional design process of ASIC cannot meet the complexity of the systematic requirement and urgent requirement to be on the market. The design process of digital chips has to transit from focusing solely on the functional realization to block-realized IP core design– SOC integration. The challenge to design now is gradually switching from the design of functional block to the evaluation, verification and integration of blocks of software and hardware. CPU, DMA and various functional blocks are integrated on the SOC. So it's a big challenge for the design engineers to find a practical way to combine these blocks effectively and meet the system requirement. At the mean time, it should not cost larger area and higher loss than the traditional method. This article takes BTV3000 as a chip design examples, discusses and analyzes the methods of SOC design.The first step for the design of SOC is the analysis of the feasibility of being on market. Then we can get a quick review of the system, bus architecture and access method can be derived. The article will give measurable analysis of required amount of data during the normal operation of each block.Our design of BTV3000 is a decoding chip based on transmit stream of digital TV. This article is concentrated on the proposal of the most effective way to design the bus architecture, which can solve the access conflict of the system perfectly and doesn't bring extra increase of area and loss. The proposal is based on the measurable analysis of the required amount of data during the normal operation of most critical IP core such as MPEG2 decoding IP core, Demux IP, etc. This proposal is also cost-effective.The systematic verification of SOC is a problem for the industrial world. At the end, article will introduce the design tool Seamless from Mentor as a verification platform for the Co-simulation. The realization of the function of the system during the design of bus is verified.The essentiality of this research lies on how to design an architecture which can support MPEG2 decoder on MP@ML and MP@HL. Meanwhile, the architecture design may be useful for other SOC design, in the similar field.