Power Supply Decoupling Network Design And Research Of The Core-M Platform Motherboard

With the rapid development of semiconductor, modern electronic systems are working towards high-power, lower voltage, heavy current, high density. The CMOS process now has reached 14 nm node, and will be reach to 10 nm at the near future quickly. At the same time, with the appearance of system on package, accelerate the speed of the multi-chip and multi-system integration technology, on the other side, the system integration degree is increasingly improved and electronics industry is moving gradually toward the More than Moore's law. Because of the improvement of system integration, the power integrity showed from the system became increasingly serious. Integrated circuit composed by plenty of transistors, and the transistors consists of the logic circuits in it, for example, gate circuit, combinational logical, state machine and so on. When the logic circuit simultaneous working, the transistors integrated in the circuit will simultaneous switching, as a result, the power supply network need to supply large current to the integrated circuit. If the power supply network impedance is too large, it will cause to DC power drop and the power supply to IC will not be stable. As a result, lead to the timing sequence and the stability of the integrated circuit go wrong. On the other hand, if the power noise resonance in the power and ground plane, it will lead to EMI effect. If the layout in the high-speed circuits mismanaged, it will lead to EMI problem at the same time.The high-speed circuit researchers have been transferred their key items to power integrity field. Power decoupling network as one of the power integrity problem is the most disagree aspect in the expert eyes and it also become the bottleneck to the engineer when they design high-speed circuits. The design of decoupling network mainly focused on the configuration and place of decoupling capacitors. After proposed the defaults of the buck circuits on Core-M platform mother board, this paper focused on research and discuss of the characteristic, configuration and place method of the capacitance in the high-speed power supply network, the decoupling network method based on target impedance, introduce and research the origin reason of EMI and optimization method. And take the Wi Fi circuit as example to explain how to optimize the EMI on the mother board at last. This paper researched and discussed the following aspects:(1) Introduced the development of the electronic products at Moore's law, the challenge faced by power integrity, the significance of the subject and the power integrity development status at home and board.(2) Summarized several questions related to power integrity, mainly concluded the definition of high-speed circuits, the reason and damage produced by power source noise, the theory of transmission line and two typical kinds of transmission on print circuit board, the definition of target impedance and the theory of decoupling network based on target impedance.(3) Discussed the structure and timing sequence of the Intel Core-M platform power supply network. Specific introduced the theory and the advantages and disadvantages of the buck circuits.(4) Thoroughly analyzed the characteristic of the capacitance in high-speed circuits decoupling network, introduced the method of configuration, placement, installation of the capacitors in decoupling network. Based on this and the theory of target impedance, and then made the target impedance method to design the decoupling network of the LPDDR3, used the allegro PCB PI tool in cadence to verify the validity of this method at last.(5) Tracing the produce source of EMI, and then analyzed from the structure of the mother board and the high-speed circuits power supply network, summarized the method to optimize and suppression EMI, and verified it.Overall, this paper based on the method of target impedance to design high-speed circuits decoupling network, according to the requirement, given out a reasonable design and simulation verification to the LPDDR3 power source decoupling network of the Core-M platform mother board. On the other hand, according to experience, summarized a method about how to control the EMI of high-speed circuits, and verified the correctness in practical test.