Characteristic Analysis On Short-circuit And UIS Of SiC Power MOSFET Device

Among the wide band-gap semiconductors,silicon carbide(Si C)is going to be used for high-power electronics applications because of its unique physical properties,such as a high critical electric field,a high thermal conductivity,and a high saturated electron velocity.Due to its material properties,Si C MOSFETs are designed with smaller thickness in the gate oxide and higher electric field compered to Si MOSFET.That make Si C MOSFETs have lower power loss and faster switching than Si MOSFET.The Commercial of Si C MOSFET can enable rapid penetration of silicon carbide MOSFET technology into applications presently dominated by silicon IGBTs.So nowadays,Si C power MOSFET is gradually used in several power applications such as inverter for PV panels and grid,UPS and railway traction drive,various Si C MOSFET device design an impression,specific optimization design according to different usage scenarios,such as integrated JBS Si C MOSFET(JMOS)in the new device can greatly reduce the MOSFET parasitic body diode as a result of high frequency switch loss,and can save external fly-wheel diode,thus further cost savings.Although JMOS has outstanding performance while achieving a high power density,the ability to guarantee reliability and safety becomes critical.At present,the short-circuit(SC)withstand capability test and the single pulse avalanche ruggedness test are the most common methods to evaluate the ruggedness of Si C MOS devices.In order to use Si C MOSFETs at the same voltage and current as Si IGBTs,Si C MOSFETs need the same or higher levels of breakdown durability and reliability.Therefore,we need to understand the avalanche mode,high power density operation or device failure mechanism under high voltage in order to modify or optimize the device structure.In this thesis,in order to identify the critical limiting factors responsible for the failure modes of SC and unclamped inductive switching with a 1.2-k V Si C JMOS,the SC and UIS test platform has been designed and built and the silvaco TCAD has been used to identify failure mechanism by modeling and simulation studies.When comparing VDMOS and JMOS devices in the SC test study,we find that the leakage current of the JMOS is much higher than that of a common VDMOS.During the SC test,the JMOS drain current cannot be successfully suppressed after gate turn-off,and the thermionic emission current due to heat generation in the Schottky barrier diode(SBD)region continues flowing into the n-drift region.The SBD thermionic emission current is rapidly increased by the increasing lattice temperature,which can reach over 1600 K.Eventually,the JMOS undergoes thermal runaway due to positive electrothermal feedback.The key to improving the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.Finally,the single UIS test of JMOS and VDMOS have been taken and we find that the Energy Avalanche Stress(EAS)of JMOS is lower than that of VDMOS with same current and voltage level.A Focused-Ion Beam(FIB)micro-section has been performed to observe the different failure locations in the vicinity of the hot spots.The failure mechanism is studied by TCAD Mixed Mode simulations to fit the UIS testing condition.The measurement and simulation results show that the damaged area of JMOS devices is significantly different from the VDMOS.There are Schottky contact failure for JMOS devices and Ohmic contact failure for VDMOS devices.