Research And Implementation Of SoC FPGA Packaging Algorithm

With the rapid development of field programmable gate array (FPGA) the transistors feature size has scaled down into nanometer scale. The computer aided design (CAD) software is faced with the requirements to cooperate with the hardware. Packing module is an important component of the CAD software, it influences the performance of the entire software. Based on research and design of 65nm SoC FPGA hardware, the paper discusses how to improve applicability and versatility of the performance of complex FPGA via packing module., meanwhile, it proposes a timing-driven packing algorithm suiting for the structure of the complex hardware.To apply for modern complex FPGA architectures, this paper makes use of the idea of CSP graph pattern matching algorithm and T-VPack algorithm. The algorithm has its versatility and flexibility to a high extent and can keep pace with the updating speed of hardware, which substantially enhances the universality of packing module. The paper also provides reasonable pattern circuits to finish packing process. With large numbers of functional simulations and verifications of test cases, the packing module is proved to be supportive of the hardware architecture of the chip.As for the software implementation, this paper designs a series of optimization strategies. Prior to packing complex logic circuits, advanced logic sub-circuits is optimized into more unified ones, which effectively reduces the number of pattern circuits. Meanwhile, in order to further optimize the area of the circuit, a compression for registers which meet the netlist constraints is adopted in this paper.With regards to the timing analysis of the circuits, this paper proposes a modern complex FPGA architecture suited timing analyzer. On the basis of the idea of T-VPack algorithm, and with timing parameters calculated by timing analyzer, packing module can optimize the performance of timing reports of circuits.The experiments show that:this module is properly applied for complex SoC FPGA. After the register compression, to those test examples with greater than 50% of resource utilization proportion, the average compression ratio can reach 4.99%. Contrast to non-timing driven packing, results of timing driven algorithm gain a 4.18% increase in average.