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Research On Layout Algorithm Based On The Optimization Space

Posted on:2017-09-16Degree:MasterType:Thesis
Country:ChinaCandidate:S S ZhiFull Text:PDF
GTID:2348330488472883Subject:Engineering
Abstract/Summary:PDF Full Text Request
With the development of modern science and technology, integrated circuits(IC, Circuit Integrated) manufacturing technology has been applied to all aspects of production and life, the function of continuous improvement and strong push forward its design process to the nanometer node, how to ensure the reliability of the circuit function and higher finished product rate has become a research hotspot. The layout phase of physical design contains the most abundant and the most accurate information. It is an important method to analyze and optimize the finished product rate of the layout in the circuit design phase. The key area of the layout and the optimization space of the line network is the important reference information in the actual layout optimization. In this paper, a method of extraction the optimal space based on morphological algorithm is designed, and the storage structure of adjacency list is presented. And finally, the layout algorithm based on the optimization space is presented.The optimization space of the line network is important reference information in the process of the actual layout optimization. Optimization space refers to the space where line network can widen or mobile with the rules of the integrated circuit layout and the key area constraint, it is a characterization of the line network can be optimized. In this paper, the method based on morphological algorithm can be used to extract the moving distance of line network and the get the optimal space of the line network, and the storage mode of the optimization space can be designed by using the graph theory: the adjacency list storage structure.The implementation of the adjacency list storage structure is introduced, and then by comparison, it is found that the adjacency list storage structure has great advantages in performance.In the process of circuit design and manufacture, the defect distribution is random. In order to reduce the critical area caused by random defects, an automatic optimization layout method based on the optimization space is proposed. The characteristic of the method is to detect the optimal space before optimization, and then carry out the process of open circuit and short circuit automatic optimization combined with the sensitivity of the line network. The method presented in this paper can detect the characteristic information of key areas which is different from the previous way with the overall widening or moving on line network, according to the characteristic information and the optimization space, the local automatic optimization of the line network is realized under the condition of meeting the design rule, so as to achieve the maximum optimization effect. Experimental results show that the proposed method can achieve accurate optimization of small key areas, and avoid the overall movement of the line network, save the routing resources, and have the guiding significance to the optimization of the layout.
Keywords/Search Tags:integrated circuit, yield estimation, optimization space, storage structure, key area, layout optimization
PDF Full Text Request
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