Research On The Yield Estimation And Optimization Based On Surrogate Circuit Model

After Integrated Circuits (IC) technology was scaled into Nano-level, the relative variations in process parameters have been continuously increasing. This severely affects the parametric yield of ICs. In addition, smaller feature size, more complicated device models, and larger circuit scale have increased the cost of circuit physical simulations so much that the runtime needed in Monte Carlo yield analysis and optimization mehtods based on circuit physical simulations becomes formidable. In order to solve these problems, this thesis proposes yield estimation and optimization methods based on Surrogate Model of circuit performance. In aspect of parametric yield estimation, this thesis proposes a novel algorithm based on quadratic response surface surrogate model, whose efficiency and accuracy are much better than traditional algorithm. This method is appropriate for extracting the parametric yield of large scale ICs, where numerous process random variables are involved. In aspect of parametric yield optimization, this thesis proposes a method based on response surface model. Compared with traditional parametric yield optimization based on parametric yield estimation, the computational cost of the proposed method can be much smaller. The effectiveness of the proposed methods has been demonstrated in several circuit cases.