Integrate Circuit IP Protection Approach Based On The Diversity Of Data-path Delay

With the rapid development of semiconductor technology, the integration and complexity of the large scale integrated circuit system is higher and higher, and design is more and more difficult. IP reuse technology has been widely used because of improving the design efficiency, and reducing design risk and costs.The development of the IP cores needs to invest a large amount of money and labor. With the promotion of IP reuse technology, IP infringement becomes the main problem in the So C design. IP replication and illegal sales not only harm the interests of the IP designer, but also reduce innovation enthusiasm. Effective protection of IP cores is highly desired in the So C industry.This article proposes an IP protection method based on data-path delay diversity. The investigation has been carried out in three steps. Firstly, the data path delay diversity is studied, and the IP core design space is formulated through the combination of modeling and optimization methods. Secondly, a hardware IP core protection method is proposed based on the data path delay. A protection circuit is designed and inserted beside the data path under protection. The delay of the protection circuit is compared to that of the data path. If the delays are not matched, then the computation result of the data path is locked, and the IP core does not work properly. A key is used to control the delay of the protection circuit. This method protects IP hardcore form various IP attacks, and ensures the rights and interests of the designers and consumers. Finally, IP protection is considered as the optimization goal of integrated circuit design. A multi-objective optimization is formulated to trade off speed, power, area and IP protection robustness. The proposed approach has been evaluated, and the experimental results proved that the IP protection approach based on data path delay diversity is effective and reliable.