Research On Hardware Security Techniques Based On Hardware Metering And Hardware Watermarking

With the prevalence of the reused-based IP technique in the semiconductorbusiness, IP theft, piracy and overbuilding are emerging as an increasingly threat forIP right owners since billions of loss are introduced by such issues every year.Therefore, research focused on IP protection techniques is of growing importance inrecent and coming decades. Hardware metering refers to those security methods orprotocols that allow the IP designers to have post-silicon control over their designedICs, and thus protect their legal IP right. Hardware watermarking is emerged as anovel technique that aims to protect designers’ IP cores by embedding a signature intoeach IP core for verification of authorship. Therefore, it is of great significanceinvestigating highly secure hardware metering scheme with low overhead，and highlyeffective watermarking extracting techniques from bitfile level. Principlecontributions of the essay include:1. Security and overhead are the key issues of active metering scheme. Toimprove the security level against brute force attack of the active metering scheme,we proposed a hierarchical FSM (HFSM) structure combined with PhysicallyUnclonable Functions (PUFs) to form a unique locking structure for eachmanufactured IC. Each IC chip begins from a fixed locked power-up state. The ICmanufacturer has to send the unique PUF response of each manufactured chip to thedesigner, so that the designer will give the unique keys and the rest FSM transitionalinput bits back to activate the chip. The proposed HFSM structure uses the PUFoutputs to determine the transitional path and then the rest input bits are utilized toimprove the security of the structure against the brute-force attack. Compared withthe related existing metering structure, the proposed scheme is more robust againstbrute-force attack and experimental results show that the overhead of the proposedscheme is acceptably low. Experiments are conducted on the Berkeley SIS platform tostudy and compare the area, power and delay overhead of the two schemes.Experimental results on the MCNC’91benchmarks show that the proposed schemehas acceptably low overhead cost.2. Many of existing watermarking techniques usually need to manually extractmarks from binary bit-files by the FPGA tool or exhaustive search to find out marks inthe design, which results in inefficiency of the watermark verification. We proposed a method to fast verify the authorship through extracting the content of the watermarkedlookup tables from a binary bit-file.