A Study On Hardware Intellectual Property Protection Based On Finite State Machine

With the growing demand for more functionality,smaller size and higher performance,designing and manufacturing such a sophisticated and size-minimized IC product requires a large amount of time and money investment.To reduce cost and shorten time-to-market,The IC industry has introduced reuse based IP paradigm that is becoming prevalent these days in the industry.Unfortunately,IP-reuse mechanisms possess various vulnerabilities in the face of different forms of IP piracy,presenting great challenges in protecting the rights of all the entities in the design model.Indeed,IP piracy has emerged as the most pressing threat in the industry,leading to tremendous loss every year.As reused IP cores usually experience both the IP evaluation period where the IP core is evaluated and verified by potential clients,and the after sale period where the IP cores will be put into production,techniques protecting reused IPs must be able to defend possible IP infringements during these two major stages in the design flow.In order to maintain the rights of different parts in the scheme of reused IP,this paper not only dedicates to the research of pre-sale and after-sale parts of IP core design but also low hardware overhead and high security robustness IC metering scheme,the main contributions of this article include:1.This article proposed a new FSM-based metering structure which has an improved robustness against the brute-force attack with lower area and power overhead.The key idea is to design a hierarchiacal FSM or a boosted hierarchial FSM to join the original circuits,then a fixed power up state is defined.In this structure,the PUF is introduced to the IC sothat each chip has a unique unlock key due to the uncloneable responses.Because of the new structure,the chips will not be able to enter the original state after fabricated.At this time,the factory has to turn to the IP designer to acquire the key to unlock each chip,and the designer will charge the fee based on the amounts of chips.In this way,the counterfeits are effectively controlled.Experiments are conducted on the Synopsys DC to study and compare the area,power and delay overhead of the two schemes.Experimental results on the MCNC'91 benchmarks show that the proposed scheme has acceptably low overhead cost with average improved robustness of 250 against the brute-force attack in 5 to 10 layers.2.This acticle also proposed a comprehensive scheme for IP protection.In the proposed framework,pre-test path was added to the improved hierarchical finite state machine structure for protecting pre and after-sales versions of IP cores.In this scenario,instead of the original way of Hardware Trojan insertion,this article introduce a non-functional defect.When the attacker pre-version of the IP core used in industrial production and use,the chip will produce unusually high power consumption.Experiments on MCNC'91 benchmarks show that non-functional defects can effectively protect the IP core at very low cost,and it is easy to get a high power to area ratio through a ring oscillator.