The Design And Research Of MCU IP Core Based On FPGA

The thesis first analyses MCU which is based on the technology of RISC and finds out that it is difficult to design the inner control logic using pipelining to improve the executive efficiency of instructions. To simplify the design of the controller, a systematical and embedded analysis of MCS-51 has been carried out in this thesis. It has been found out that the key factors of affecting its performance are the ALU structure based on accumulator, the CISC architecture and the time of executing instructions.Then a characteristic Micro-Controller core is presented. The core mends traditional 51 series MCU on structure, instruction system and instruction time. The performance of designed MCU has been greatly improved by adopting Harvard architecture, single-phase clock and synchronous design.The designed MCU IP soft core which is written by VHDL has many outstanding traits and favors the SOC design based on IP duplicate technology. Various EDA tools are used to verify the whole Micro-Controller core. It is shown that the MCU core's maximum clock frequency and instruction execution speed are three times higher than traditional MCS-51 core.