System Design Of High-speed Image Capture And Compression Storage

With the rapid development of internet and digital multimedia technology, people put forward new requirements for the speed of data transmission. Image data occupies vast part of bandwidth resource in storage and transmission pro-cess, therefore, image compression technology becomes more important than before. FPGA is an ideal platform for realizing image compression technology. This paper just specializes in designing the method of image acquisition com-pression and storage system based on the platform of FPGA.In this paper, three main parts of the system were designed and imple-mented. The part of image acquisition using high speed digital cameras capture images, according to Camera Link protocol timing, this paper designs the Cam-era Link hardware circuit. The image compression part using JPEG image com-pression standard, to use the symmetry of 2D-DCT transform coefficients and the pipeline characteristic of FPGA. This paper put forward a fast 2D-DCT al-gorithm to save system running time, low computation for apply in engineering. This algorithm let the DCT coefficients sharing assignment in different times, continuously doing twice DCT transform to realize seamless processing of data. Quantization module division data previously stored in memory, and by means of look-up table, the division is converted to multiplication. Entropy coding module using Huffman coding, DC coefficients and AC coefficients are encoded by the variable-length data registration code into fixed length output code to obtain a final Huffman code stream. Image storage module design SDRAM read and write timing to let compressed image data stored in the storage resource.In the scheme of this paper, under circumstance of amply on-chip resources, I process the compression module in ping-pong operation to increase the pro-cessing speed of the system and data throughput. In this way, the time continuity of image data processing is guaranteed, and the real-time requirement of the system is achieved.The whole system is realized with Verilog HDL programming language in the designing environment of ISE 14.6 of Xilinx Inc. The hardware platform is Virtex-6 development board and each module and the whole system are tested on this board. With ModelSim simulation tool the testing results show that the compression performance of the system can meet the practical requirements.