Research And Implementation Of Digital Baseband For WSN Wireless RF Transceiver

Wireless Sensor Network(WSN) has wide market prospects, but the large size, high power consumption and high cost of sensor node limit its large scale use. RF transceiver is the bottleneck of low-cost and low-power sensor node design and its digital baseband has always been a research focus in the field of wireless communication. This dissertation investigates the feature and application requirements of WSN and finishes the following works.Firstly, based on the design specifications of Digital Baseband and the structure of RF transceiver,which are determined by studying the technical features of WSN-related standard protocols, domestic and foreign technical literature as well as commercial chips, the architecture of Digital Baseband is proposed.Secondly, based on the study of GFSK modulation and VCO open loop modulation transmitter, the structure of digital baseband modulator using look-up-table method is proposed. The modulator converts baseband data to an analog GFSK signal which directly modulates the output frequency of VCO. It can be seen that the proposed modulator has simple structure, which is low power and low cost.Next, based on the study of Low-IF receiver, the structure of digital baseband demodulator using Time-to-Digital Converter technique(TDC) is proposed. The demodulator has the simplicify of analog demodulators as well as the stability of digital ones, and ensures the demodulation performance with reduction of cost and power consumption. The BER theoretical analysis model for the proposed demodulator is presented with the affect of channel noise,.etc, which proves the feasibility of the design and plays a guiding role for the design of channel filter.Then, based on the study of data frame, spread spectrum and interface bus, the processor interface is designed, which is responsible for the communication between microprocessor and Digital Baseband.Finally, based on these studies, the circuit and layout design of digital baseband is realized in HJTC 0.18?m CMOS technology with the power consumption of 3.24 mW and the layout area of 0.395mm2, which meets the requirement of low power and low cost.The simulation results show that signal-to-noise ratio of the proposed modulator is more than 40 dBc with frequency offset of 2MHz and more than 60 dBc with frequency offset of 3MHz, the demodulator achieves BER of 0.1% with Eb/N0 of 10.8dB and the processor interface can ensure the normal communication between Digital Baseband and microprocessor.