| A baseband digital processor which will be incorporated into a low-power frequency-hopped spread spectrum (FH/SS) transceiver for 902-928 MHz ISM band applications is described. The implementation of the baseband processor is partitioned in two parts: a custom CMOS baseband receiver chip and two field programmable gate array (FPGA) chips for low data rate, application-specific baseband processing. The baseband receiver IC performs noncoherent binary/quaternary frequency shift keying (FSK) demodulation, equal-gain diversity combining of dual antenna branches, and symbol and frequency synchronization. This chip accommodates variable data rates from 2-160 kbps, programmable hop rates, and tunable bandwidth loop filters. The core area of the 1-{dollar}mu{dollar}m CMOS chip is 3.9 mm x 3.9 mm with a power consumption of 4.5 mW from a 3-V supply at 10 MHz. Two XILINX FPGA chips with approximately 14,000 total gates implement the remainder of the baseband transceiver functions for the prototype, including frequency control logic for FSK modulation, acquisition control, data framing, symbol interleaving and deinterleaving, and interface control for data and voice inputs. |
