Design And Research Of Analog Baseband For WSN Transceiver

With the rise of various interdisciplinary research and the development of Internet of Things (IoT), the Wireless Sensor Networks (WSN) not only draws attention of major universities and research institutes in academia, but also shows a very competitive market performance and huge market potential in industries. The WSN now is increasingly being used in civilian areas, such as health care, industrial monitoring and smart city, which has broad prospects for development. WSN nodes own the characteristics of large-scale network and complex distribution environment, which causes the design of low-cost, low-power and highly integrated wireless transceiver becoming a hot spot of research. Duo to the power consumption and chip area of analog baseband occupies a large proportion in the whole transceiver, its low-power and highly-integrated design is of great significance for WSN applications. Therefore, based on IEEE 802.15.4 standard and ZigBee technology, this paper completes the study and design of an analog baseband circuit in the 2.4GHz wireless transceiver.In this paper, characteristics of ZigBee technology and the development of its application in WSN are described systematically. Based on research and production status of ZigBee wireless transceiver in recent years, the design goal of low-power highly-integrated analog baseband is proposed. The concept and significance of performance index of wireless transceiver are introduced carefully and a detailed mathematical deduction is carried out, then obtaining the calculation method of the key performance index. Finally, according to the requirement of 802.15.4 IEEE protocol and the function characteristic of each circuit module, based on realizability of circuit, the design specifications of each circuit module in analog baseband are presented. A 3rd-order Butterworth complex band-pass filter (Complex BPF) is designed to solve the problems for traditional band-pass filter of symmetric frequency response on the frequency axis. The BPF presented in this paper can realize the required design functions of channel selection and image rejection in Rx chain. A mixed-signal frequency auto-tuning scheme is proposed for complex BPF to accommodate the performance deterioration due to the process, voltage and temperature (PVT) variations. The frequency auto-tuning scheme is composed of a ring oscillator and a successive approximation (SAR) digital algorithm, which ensure the accuracy of the frequency response. A variable gain amplifier (VGA) is presented in this paper. The VGA coarse gain tuning stage is composed of four cascade fixed-gain amplifier (FGA) by ac coupling. The programmable gain amplifier (PGA) is designed for fine gain tuning, which provide the gain step adjustment by controlling the resistance ratio of feedback network. A 7bits 16 MS/s pipelined analog-to-digital Converter (ADC) is designed in this paper. A novel method named "time-sharing" that combined opamp-and capacitor-sharing is proposed. It utilizes different setup time of two operational amplifiers to eliminate the memory effect and improving the overall performance for ADC while reducing the chip area and power consumption. A 6bits 16 MS/s current-steering digital-to-analog converter (DAC) is presented in this paper. Discussion of its static/dynamic performance and power/area is done for different segmentation scheme, and finalized 4+2 structure. According to analysis for the influence of the current source output impedance and the non-ideal switching signal on DAC performance, a high-output-impedance current cell and a low-dynamic-error switch driver are presented. A 4-th order low-pass filter (LPF) is designed by cascading two stage of biquad structure, which can suppress high frequency harmonics for DAC output signal effectively.The analog baseband proposed in this paper is implemented in TSMC 0.18μm 1P4M 1.8V CMOS process. After layout designing and post-simulation, the whole WSN wireless transceiver has been tape-out and test. The test results show that the center frequency and bandwidth of BPF are 2.07MHz and 2.93MHz; adjacent channel attenuation, alternate channel attenuation and image rejection are 34dB,46dB and 24dB; input third-order intercept point (IIP3) and noise figure (NF) are 18.7dBm and 28.5dB. The total gain rage of VGA is 70dB with gain step of 2dB; the gain error is 0.52dB; IIP3 and NF are -18.8dBm and 28dB. The pipeline ADC shows the differential non-linearity (DNL) of 0.53LSB and integral non-linearity (INL) of 0.72LSB; the signal to noise and distortion ratio (SNDR) is 39.51dB; spurious free dynamic range (SFDR) is 50.48dB; effective number of bit (ENOB) is 6.27bits. The current-steering DAC shows the DNL of 0.34LSB and INL of 0.47LSB; SNDR is 29.87dB; SFDR is 34.8dB; ENOB is 4.7bits. The cutoff frequency of LPF is 1.37MHz, and stop-band attenuation is 47dB@16MHz. The chip area and power consumption of Rx analog baseband is 1.56mm2 and 16.99mW. The Tx analog baseband show the chip area of 0.24mm2 and power consumption of 7.58mW.