Design And Implementation Of The Backplane And Switching System Of A Reconfigurable Image Processor

With the constant development of the electronic hardware technology and based on the fact that parallel image processing system of DSP processor array has been widely used in areas such as nation’s defense, industry, biology, communication etc, the image processor is becoming smaller, high-speed and more concise. Due to the demand for multi-area digital image processor of different content, different characters, the function of image processor can be mainly reflected in complicated and flexible processing and calculating, the high throughput data transmission and the real time in practical application. This requests the hardware platform, having a processor with strong calculating capability, should be facilitated with a flexible and efficient data exchange framework so as to realize the upgrading of image processor’s comprehensive performance.The paper, based on PCIe, SRIO, Gigabit Ethernet multi high speed bus switching chip, designed and completed multi protocol interface switch board; and, based on 3U backplane of VPX bus and structure standard and through using a variety of high speed serial bus and protocol switch chip, has the host computer communications and the control bus accessed to the processor data channel which makes the host computer available to constantly monitor the bottom processing state, and set up the high efficiency and low redundancy star-like interconnection topology structure of data line between processor array that have the data line of DSP processor array for host computer and multi image processing board flexibly connected, and then have the dynamic allocation of the image processor and online code update applicable for image processing machine, and eventually realize the real-time reconstruction of DSP array.The paper also analyzed the design and realization of function card of image processor, including CPU system board based on X86 framework CPU as system host computer and large power supply board for whole machine, and proposed the hardware design plan for each card. In addition, the machine used a variety of high speed serial bus for high speed transmission; focus on the signal integrity design for high speed signal, while working on PCB design for each card, guarantee the system performance. Moreover, in order to ensure the follow-up R&D of overall unit of the image processor, the paper also proposed, based on a double chips DSP processor TI TMS320C6678 system with leading performance a complete design plan for image processor and dot design of VPX high speed bus guarantees the universal of the card.Moreover, in order to ensure the follow-up R&D of overall unit of the image processor, the paper also proposed, based on a double chips DSP processor TI TMS320C6678 system with leading performance a complete design plan for image processor and dot design of VPX high speed bus guarantees the universal of the card.Last, the completed boards underwent comprehensive function and performance test by variety of instruments and equipment, and the whole unit accomplished joint debugging, the result of which fully confirmed the switching function of dynamic re-configurable image processor and the performance met the parameter.