Research And Implementation Of Contactless CPU Card Bootloader And COS

Contactless CPU card includes Bootloader and COS(Chip Operating System), which has powerful data storage and processing capabilities as well as abundant peripheral software interface, due to which its application is becoming more and more popularly. Based on the hardware system of contactless CPU card chip BES1426 which was designed by Beijing Embedded System Key Lab, the research work in this thesis has developed related Bootloader and COS program. Thus, a whole set of software system in smart card chip is built here to meet the financial application standards of PBC2.0(The People’s Bank of China) to be used as electronic wallet/electronic passbook. Meanwhile, combining with the Bootloader and COS built in this thesis, the BES1426 smart card can be applied in financial, transportation and medical area. Thesis research work has a significant research and practical value.The main research work of this thesis revolves around the Bootloader and COS. First of all, On the foundation of BES1426 V12, this work has been performed utilizing the development language of C51 and integrated development tool of KEIL. A promotion design of the system is realized based on the software design in the chip that has already been taped out, and the functional testing of the new design has also been done in FPGA platform. Secondly, as about the software system design, this work has designed the Bootloader as well as the COS which meets the international standards of ISO/IEC14443, to achieve the application of electronic wallet/ electronic passbook in PBC2.0 specification. Finally, a complete system test plan, which uses the reader developed by the Lab as well as the test platform supplied by the third party, is also proposed in the thesis.The innovations of this work include the design of Bootloader in smart card and the related auxiliary parameters adjustment, the design of patch mechanism of ROM driven code and high efficient data backup mechanism in EFLASH, the design of high speed down load COS which is also of upgradability and download- repeatability and the anti-plug design for EFLASH.The BES1426 chip was taped out in SMIC180 nm Embedded EFLASH CMOS process. After being packaged in to smart card, several tests were gone, aiming to check work function, reliability, transaction flow as well as security performance. The test results show that the proposed design of this thesis is feasible. The design plan and research results of the thesis have very good reference value both for the design of embedded system and for the develop design of smart card software system.