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The Research And Simulation Of Embedded RAM Testing

Posted on:2009-11-10Degree:MasterType:Thesis
Country:ChinaCandidate:Y SongFull Text:PDF
GTID:2178360242990461Subject:Electrical engineering
Abstract/Summary:PDF Full Text Request
With the increasing of the IC design and manufacturing technology, the integration and complexity of chips keeps increasing in accordance with Moore's LAW. Especially the VDSM technology is usedm, the faults become more and more types and difficulty to test on the production process. Chip testing issue meets unprecedented challenges, has become a bottleneck restricting the development of the whole industry. In such circumstances, considering from the fault types, test equipments and testing costs, the DFT technology becomes a principal means to solve the chips testing problem, is paid attention gradually by people.The thesis is about the embedded RAM testing, researches solution. First, the thesis introduces the digital IC, memory and testing technology development status and trends, describes the memory basic structure, categories, failure model and fault models. Then, the thesis researches and analysis memory testing methods, the algorithms which generate the test pattern graphics. The algorithms are described according to the relations between test pattern graphics'length and memory size. These algorithms, the complexity and fault coverage are both different. It analysis the March algorithm in details, and this algorithm has been developed into a kind of word-oriented algorithm.The IC integration is more and more big; it causes the big testing expense and testing access difficult. BIST (Built-In-Self-Test) is considered for a technology which can solve these problems. The thesis uses MBIST for RAM testing. MBIST is widely used in the mass memory testing. The BIST logic circuit is embedded in the chip, on chip BIST structure. The BIST controller, address counter circuit, the data generator circuit and the response compare circuit have been implemented respectively, the test is automatically run on the chip. The BIST structure and a RAM which is added in many kinds of faults have been simulated with VHDL, use March C algorithm. The result shows the method can cover most faults, it testifies the validity of the MBIST testing based on March algorithm.
Keywords/Search Tags:Embedded memory, Design for test, Memory Built-In-Self-Test, March algorithm, VHDL
PDF Full Text Request
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