The Design And Implementation Of Packet Reassembling Circuit Of Optical Transport Network

As the hign bandwidth needs of business enrichment, OTN which is the most suitable for larger particles transmission and IP optical transmission network arises at the historic moment and reduces the network construction cost effectively. In view of the current OTN switching technology, the packet switching technology is widely used. Converting OTN particles into a whole package of business data transmission format, it’s core function depends on the SAR(Segmentation and Reassembling), and the priciple of segmentation and reassembling is applied to OTN exchange. On the basis of studying the OTN packet reassembling key technologies deeply, the paper achives reassembling packets as a continuous data stream.On the basis of in-depth study application requirements, the specifications and the overall scheme are finished in the OTN packet-switched circuit interface chip packet reassembling circuit. The interface chip specification defines the function and performance indicators of the circuit. While the overall design scheme defines the timing between the circuit and the Interlaken interface, and the timing between the circuit and multiplexing interface, the circuit is divided into sub-modules.On the basis of the overall design sheme, the paper finishes the detailed design scheme of the circuit. In the scheme, the three problems are mainly solved. First, how to achive transmitting data services between several clock domains, this paper mainly uses the asynchronous fifo to solved this problem. Second, different ODUk in different time intervals, reassembling of fixed size±1 packet, how to complete within the given time data to send, depending on the state machine in the design of the scheduling of data. Third, its OTN system for ODUk packets in the process of packet loss and packet redundance, sends data information effectively and improves the efficiency of data transmission. On the basis of the detailed design scheme, the hardware description language Verilog is used to implement the various modules. Then using the circuit simulation tool Questa Sim-64 10.1d and the synthesis tool called Quartus Ⅱ 13.0. Finally, based on DE5-Net development board, the design circuit and NiosⅡ soft core architecture relize FPGA hardware circuit testing.Experimental results show that the circuit can meet the function of the technical specifications and the requirements of the technical indicators, and improve the work performance of the entire OTN data packet switching platform. Finally, comparing with the PMC company recently launched the first 400G OTN DIGI-G4 chip processor in performance, and comparative results indicate that OTN packet switching circuit has a good prospect and achieves 1G,2.5G,10G packet exchange business, but does not still support the exchange of 40G/ODU3,100G/ODU4 particles and can further improve the business.