High Speed Data Interface In Optical Packet Switching Edge Node

With the explosion of the global information services, the traditional telecommunication network architecture fails to meet the development of new services. Transportation oriented bottom optical transport layer is evoluting to switching oriented optical network layer. As the key technology of next generation all optical network, Optical Packet Switching is nowadays hot in this research field. That OPS conquers the"electronic bottleneck"in the current network transportation makes it to be the promising solution of next generation network.In this paper, we focus on the design and implementation of FPGA in Optical Packet Switching edge node based on the project in the laboratory. We have finished some fundamental work aiming to build the edge node FPGA platform.First we introduce the Optical Packet Switching network including network topology, key technology, function and structure of core node and edge node. Finally, we reach the network processor and FPGA platforms in the edge node.Then we discuss the design and implementation of SERDES which is important in our project. At the beginning, we give some key technology in SERDES design, such as SERDES principle, 8B/10B encoding/decoding, word and channel alignment, LVDS high speed differential signal. After the design specification is determined, we focus on the modules in SERDES ranging from function and ports to technical point and special resource. Simulation results after synthesis and PAR show that SERDES is functional and timing verified and design specification is met. Finally, the pins of the chip on the development board are configured.At the end of this paper, we study the performance of packet aggregation in the FPGA. The same result is reached by both MATLAB and Verilog simulation, which verify the performance and feasibility of packet padding algorithm.