| With the rapid development of integrated circuits, the increasing complexity of design makes it more and more difficult to perform verification. The workload of verification has accounted for 70% to 80% of the entire design and development. Traditional verifi-cation methods and procedures are unable to meet current verification requirements. Ac-cording to increasingly complex verification requirements, the industry proposes the IC verification platform method based on verification methodology. By using verification methodology, it can shorten the development cycles of testbench, accelerate the verifica-tion speed, and strengthen the completeness of IC verification and save the verification cost.On the basis of studying the UVM interface module verification platform, this paper builds verification platform of I2C interface with UVM, and perform tests with simula-tions.The main work of paper are as follows:1. I2C bus interface is chosen as the research object, and studied deeply,.Master and slave modules in the I2C bus interface model are introduced.2.I2C bus interface verification platform is designed based on UVM technology. This UVM verification platform includes Driver, Monitor, Agent and other components, the top-level module, the definition of Transactions, the design of Sequence and Test compo-nents. At the same time, the cover component is designed to test the coverage and the coverage group and the coverage point are also defined.3. The basic function test, random test, error test and additional user test are carried out respectively on this verification platform. The test results show that verification platform can correctly complete the read and write basic functions; Random tests can make up part of the problem of basic function test; Wrong test can detect the content which does not meet standard I2C protocol. The additional user test can make cover rate to reache 100% which belong to a part of covering group and the overall coverage rate approach to 100%. |
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