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Research And Design Of ETC System’s Key Technologies Based On FPGA

Posted on:2017-01-17Degree:MasterType:Thesis
Country:ChinaCandidate:Z J LiFull Text:PDF
GTID:2308330488964419Subject:Computer technology
Abstract/Summary:PDF Full Text Request
As an important part of intelligent transportation system (ITS), the application of electronic toll collection (ETC) has greatly improved the efficiency of vehicles passing through the highway toll station. However, due to the current etc users have not yet been popular and part of the etc lanes set unreasonably, there are often some non-ETC vehicles drives into the ETC lanes, which leads to serious traffic jam in the toll plaza; In addition, the mechanical railings of ETC lanes make some users habitually braking the vehicle. These factors seriously restrict the further improvement of the efficiency of the highway toll station vehicles.Aiming for shortening the time of vehicles through the toll station, this paper compares the common ways of setting ETC lanes at home and abroad, and analyzes the software and hardware methods of implementing ETC system. The system improves the traffic efficiency of vehicles from the following two aspects:one is based on the analysis of type selection, setting mode and equipment layout of the lane, this paper designs an overhead of ETC lanes and lane controllers, cancels the traditional lanes railing, implements the ETC transparency to users, and effectively solves the congestion problems caused by non-ETC vehicles drives into the ETC lanes; The other is by optimizing the internal structure of ETC baseband circuit, the system uses the real-time characteristic of FPGA technology to implementation the key module of the baseband circuit and the class A baseband codec called Manchester codec of the international standard.This paper uses Quartus II 8 as the integrated development environment and Modelsim 6 professional simulation tool as the experimental platform. In the design of lane controller, this paper uses the hardware description language Verilog HDL to program, which fuses a variety of lane auxiliary equipment control signals together, and finally it achieves the purpose of high real-time performance and strong anti-interference ability; As for the design of baseband circuit, the system adopts the "bottom-up" design methods. According to the functional division module, it determines the internal structure diagram. First of all, each module is designed and simulated separately, and then the son modules will be integrated together to verify the simulation. From the simulation results, the design has reached the expected effect, which can meet the requirements of the ETC system. This design will effectively promote the further development of ETC system, and it will have a certain theoretical value and practical significance to the popularization and application of ETC system.
Keywords/Search Tags:electronic toll collection system, FPGA, lane layout, HDLC
PDF Full Text Request
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