Design Of 6.3-6.8GHz RF Transceiver Front-end Chip

For the future 5G communications, in addition to using the licensed spectrum resources below 6GHz, it will also be expected to develop and expand the use of 6-100GHz wireless spectrum resources. This design adopts 6.3-6.8GHz as the communication band. Zero-IF transceiver is adopted, and the technical specifications are determined. RF receiver front-end consists of low noise amplifier (LNA) and downconvert Mixer. RF transimitter front-end consists of driver amplifier, RF variable gain amplifier and upconvert Mixer. The targets of these cells are made explicit.LNA need to achieve single-to-differential. After comparing several common LNA architectures, the LNA uses noise-cancelling structure. On the basis of the traditional structure, the positive feedback and current reused technologies are used for optimizing voltage gain and noise figure. The balance-Buffer is used to optimize the differential output performance.In order to improve the linearity of the mixer and reduce flicker noise, passive mixer structure is selected. The mixer is I/Q quadrature mixer, comprising four switch pair circuits and two fully differential amplifiers. The output signal bandwidth is greater than 250MHz, and input P1dB is better than-5dBm.Driver amplifier design requires achieving double-to-single function, and output power should be greater than 6dBm. DA circuit is divided into two levels:the double-to-single circuit and output drive circuit. In order to improve the linearity and bandwidth, and reduce chip area, the push-pull inverter circuit structure is used as output driver stage. Double-to-single circuit adds a small inductor to balance the phase and amplitude of the differential signal. The design uses a 2.5V supply voltage to achieve linearity specifications, and the thick gate oxide transistors are used.RF variable gain amplifier design uses a fully differential Cascode amplifier configuration. To improve the linearity of the circuit, the input offset voltage needs design carefully. Changing the current flows can get variable gains, and adjustable gain is 0-10dB.The upconvertor mixer is in the form of a fully differential I/Q quadrature modulator structure, which includes two double-balanced Gilbert cell mixers. Differential inductor with a center tap is used as the load. The input offset voltage can be adjusted. The dynamic bias circuit is to achieve the LO-side bias voltage. For expanding the bandwidth, the resistor can be added in the load.The RF transceiver front-end chip achieves singal-chip integration. The chips are all designed in TSMC 0.13um CMOS process. The layout design, post simulation, tape out and chips tests are all completed. The RXFE chip measurements shows that:S11＜-10dB, the gain is 19-31dB, the bandwidth is 350MHz, the input P1dB is better than-20dBm, the IIP3 is better than-lOdBm and the NF is less than 4dB. The quadrature output signals have the good performance. The TXFE chip post-simulation shows that:OP1dB is greater than7dBm, OIP3 is greater than 20dBm, the gain is 16-26dB and the bandwidth is greater than 500MHz.